PIC18C658/CL Microchip Technology, PIC18C658/CL Datasheet - Page 125
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PIC18C658/CL
Manufacturer Part Number
PIC18C658/CL
Description
IC MCU OTP 16KX16 CAN 68-PLCC
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C770-ISO.pdf
(8 pages)
3.PIC18C658-IPT.pdf
(366 pages)
4.PIC18C658-IPT.pdf
(16 pages)
5.PIC18C658-IPT.pdf
(16 pages)
6.PIC18C658-IPT.pdf
(16 pages)
Specifications of PIC18C658/CL
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
52
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
68-PLCC
For Use With
AC164308 - MODULE SKT FOR PM3 68PLCCDVA18PQ640 - DEVICE ADAPT PIC18C658 64-TQFP
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Other names
Q1068347
- PIC16F616T-ISL PDF datasheet
- PIC16C770-ISO PDF datasheet #2
- PIC18C658-IPT PDF datasheet #3
- PIC18C658-IPT PDF datasheet #4
- PIC18C658-IPT PDF datasheet #5
- PIC18C658-IPT PDF datasheet #6
- Current page: 125 of 366
- Download datasheet (7Mb)
13.2
The Timer1 oscillator may be used as the clock source
for Timer3. The Timer1 oscillator is enabled by setting
the T1OSCEN bit (T1CON Register). The oscillator is
a low power oscillator rated up to 200 kHz. Refer to
“Timer1 Module”, Section 11.0 for Timer1 oscillator
details.
13.3
The TMR3 Register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR3 Interrupt, if enabled, is generated on overflow
which is latched in interrupt flag bit TMR3IF (PIR Reg-
isters). This interrupt can be enabled/disabled by set-
ting/clearing TMR3 interrupt enable bit TMR3IE (PIE
Registers).
TABLE 13-1:
2000 Microchip Technology Inc.
INTCON
PIR2
PIE2
IPR2
TMR3L
TMR3H
T1CON
T3CON
Legend:
Name
Timer1 Oscillator
Timer3 Interrupt
x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.
Holding register for the Least Significant Byte of the 16-bit TMR3 register
Holding register for the Most Significant Byte of the 16-bit TMR3 register
RD16
RD16
GIEH
Bit 7
GIE/
—
—
—
REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
T3CCP2 T3CKPS1 T3CKPS0
PEIE/
CMIF
CMIE
CMIP
GIEL
Bit 6
—
T1CKPS1 T1CKPS0 T1OSCEN
TMR0IE
Bit 5
—
—
—
INT0IE
Bit 4
—
—
—
Advanced Information
T3CCP1
BCLIF
BCLIE
BCLIP
RBIE
Bit 3
T1SYNC
T3SYNC
TMR0IF
LVDIF
LVDIE
LVDIP
13.4
If the CCP module is configured in Compare mode to
generate a “special event trigger" (CCP1M3:CCP1M0
= 1011), this signal will reset Timer3.
Timer3 must be configured for either timer or Synchro-
nized Counter mode to take advantage of this feature. If
Timer3 is running in Asynchronous Counter mode, this
RESET operation may not work. In the event that a write
to Timer3 coincides with a special event trigger from
CCP1, the write will take precedence. In this mode of
operation,
becomes the period register for Timer3. Refer to
“Capture/Compare/PWM (CCP) Modules”, Section 14.0
for CCP details.
Bit 2
Note:
TMR1CS TMR1ON 0-00 0000
TMR3CS TMR3ON 0000 0000
TMR3IF
TMR3IE
TMR3IP
Resetting Timer3 Using a CCP Trigger
Output
INT0IF
Bit 1
The special event triggers from the CCP
module will not set interrupt flag bit
TMR3IF (PIR registers).
the
CCPR1H:CCPR1L
CCP2IE
CCP2IP
CCP2IF
RBIF
Bit 0
PIC18CXX8
0000 000x
-0-- 0000
-0-- 0000
-0-- 0000
xxxx xxxx
xxxx xxxx
Value on
POR,
BOR
DS30475A-page 125
registers
0000 000u
-0-- 0000
-0-- 0000
-0-- 0000
uuuu uuuu
uuuu uuuu
u-uu uuuu
uuuu uuuu
Value on
RESETS
all other
pair
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