PIC18C658/CL Microchip Technology, PIC18C658/CL Datasheet - Page 281
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18C658/CL
Manufacturer Part Number
PIC18C658/CL
Description
IC MCU OTP 16KX16 CAN 68-PLCC
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C770-ISO.pdf
(8 pages)
3.PIC18C658-IPT.pdf
(366 pages)
4.PIC18C658-IPT.pdf
(16 pages)
5.PIC18C658-IPT.pdf
(16 pages)
6.PIC18C658-IPT.pdf
(16 pages)
Specifications of PIC18C658/CL
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
52
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
68-PLCC
For Use With
AC164308 - MODULE SKT FOR PM3 68PLCCDVA18PQ640 - DEVICE ADAPT PIC18C658 64-TQFP
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Other names
Q1068347
- PIC16F616T-ISL PDF datasheet
- PIC16C770-ISO PDF datasheet #2
- PIC18C658-IPT PDF datasheet #3
- PIC18C658-IPT PDF datasheet #4
- PIC18C658-IPT PDF datasheet #5
- PIC18C658-IPT PDF datasheet #6
- Current page: 281 of 366
- Download datasheet (7Mb)
DECFSZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Example:
2000 Microchip Technology Inc.
Before Instruction
After Instruction
operation
operation
operation
Decode
No
No
No
Q1
Q1
PC
CNT
If CNT
If CNT
Q1
PC =
PC =
=
=
=
operation
operation
operation
register ’f’
Decrement f, skip if 0
[ label ] DECFSZ f [ ,d [,a] ]
0
d
a
(f) – 1
skip if result = 0
None
The contents of register 'f' are dec-
remented. If 'd' is 0, the result is
placed in WREG. If 'd' is 1, the
result is placed back in register 'f'
(default).
If the result is 0, the next instruc-
tion, which is already fetched, is
discarded, and a NOP is executed
instead making it a two-cycle
instruction. If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ is 1, the Bank
will be selected as per the BSR
value.
1
1(2)
Note: 3 cycles if skip and followed
HERE
CONTINUE
Read
0010
No
No
No
Q2
Q2
Q2
Address (HERE)
CNT - 1
0;
Address (CONTINUE)
0;
Address (HERE+2)
f
[0,1]
[0,1]
by a 2-word instruction.
255
dest,
11da
operation
operation
operation
DECFSZ
GOTO
Process
Data
No
No
No
Q3
Q3
Q3
ffff
CNT
LOOP
Advanced Information
destination
operation
operation
operation
Write to
No
No
No
Q4
Q4
Q4
ffff
DCFSNZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Example:
Before Instruction
After Instruction
operation
operation
operation
Decode
TEMP
TEMP
If TEMP
If TEMP
No
No
No
Q1
Q1
Q1
PC
PC
register ’f’
operation
operation
operation
Decrement f, skip if not 0
[label] DCFSNZ f [ ,d [,a] ]
0
d
a
(f) – 1
skip if result
None
The contents of register 'f' are dec-
remented. If 'd' is 0, the result is
placed in WREG. If 'd' is 1, the
result is placed back in register 'f'
(default).
If the result is not 0, the next
instruction, which is already
fetched, is discarded, and a NOP is
executed instead making it a two-
cycle instruction. If ’a’ is 0, the
Access Bank will be selected,
overriding the BSR value. If ’a’ is
1, the Bank will be selected as per
the BSR value.
1
1(2)
Note: 3 cycles if skip and followed
HERE
ZERO
NZERO
Read
0100
No
No
No
Q2
Q2
Q2
f
[0,1]
[0,1]
PIC18CXX8
by a 2-word instruction.
255
=
=
=
=
=
dest,
DCFSNZ
:
:
11da
operation
operation
operation
?
TEMP - 1,
0;
Address (ZERO)
0;
Address (NZERO)
Process
Data
0
No
No
No
Q3
Q3
Q3
DS30475A-page 281
ffff
TEMP
destination
operation
operation
operation
Write to
No
No
No
Q4
Q4
Q4
ffff
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