PIC18C658/CL Microchip Technology, PIC18C658/CL Datasheet - Page 97
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PIC18C658/CL
Manufacturer Part Number
PIC18C658/CL
Description
IC MCU OTP 16KX16 CAN 68-PLCC
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C770-ISO.pdf
(8 pages)
3.PIC18C658-IPT.pdf
(366 pages)
4.PIC18C658-IPT.pdf
(16 pages)
5.PIC18C658-IPT.pdf
(16 pages)
6.PIC18C658-IPT.pdf
(16 pages)
Specifications of PIC18C658/CL
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
52
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
68-PLCC
For Use With
AC164308 - MODULE SKT FOR PM3 68PLCCDVA18PQ640 - DEVICE ADAPT PIC18C658 64-TQFP
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Other names
Q1068347
- PIC16F616T-ISL PDF datasheet
- PIC16C770-ISO PDF datasheet #2
- PIC18C658-IPT PDF datasheet #3
- PIC18C658-IPT PDF datasheet #4
- PIC18C658-IPT PDF datasheet #5
- PIC18C658-IPT PDF datasheet #6
- Current page: 97 of 366
- Download datasheet (7Mb)
8.5
PORTE is an 8-bit wide, bi-directional port. The corre-
sponding Data Direction register is TRISE. Setting a
TRISE bit (=1) will make the corresponding PORTE pin
an input (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISE bit (=0) will
make the corresponding PORTE pin an output (i.e., put
the contents of the output latch on the selected pin).
Read-modify-write operations on the LATE register
reads and writes the latched output value for PORTE.
PORTE is an 8-bit port with Schmitt Trigger input buff-
ers. Each pin is individually configurable as an input or
output. PORTE is multiplexed with several peripheral
functions (Table 8-9).
FIGURE 8-8:
2000 Microchip Technology Inc.
PORTE, TRISE and LATE Registers
Note 1:
Peripheral Out Select
Peripheral Data Out
Peripheral Data In
Peripheral Enable
RD PORTE
WR TRISE
WR LATE
or
WR PORTE
Data Bus
PORTE BLOCK DIAGRAM
I/O pins have diode protection to V
RE0
RE1
RE2
RE3
RE4
RE5
RE6
RE7
Pin
TRIS Latch
Data
D
D
CK
RD TRISE
CK
Latch
RD LATE
Override
Q
Q
Q
Q
Advanced Information
Yes
Yes
Yes
No
No
No
No
No
TRIS OVERRIDE
DD
Peripheral
PSP
PSP
PSP
—
—
—
—
—
and V
Override
TRIS
SS
0
1
.
Q
EXAMPLE 8-5:
CLRF
CLRF
MOVLW
MOVWF
EN
D
PORTE
LATE
0x03
TRISE
Schmitt
Trigger
V
V
N
P
SS
DD
INITIALIZING PORTE
; Initialize PORTE by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RE1:RE0 as inputs
; RE7:RE2 as outputs
PIC18CXX8
DS30475A-page 97
I/O Pin
(1)
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