AT89LS8252-12JC Atmel, AT89LS8252-12JC Datasheet - Page 15

• Manufacturer Part Number: AT89LS8252-12JC
• Description: IC MICRO CTRL 12MHZ 44PLCC
• Manufacturer: Atmel
• Series: 89LSr

Specifications of AT89LS8252-12JC

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 32
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -
• Other names: AT89LS825212JC

The interconnection between master and slave CPUs with
SPI is shown in the following figure. The SCK pin is the
clock output in the master mode but is the clock input in the
slave mode. Writing to the SPI data register of the master
CPU starts the SPI clock generator, and the data written
shifts out of the MOSI pin and into the MOSI pin of the
slave CPU. After shifting one byte, the SPI clock generator
stops, setting the end of transmission flag (SPIF). If both
the SPI interrupt enable bit (SPIE) and the serial port inter-
rupt enable bit (ES) are set, an interrupt is requested.
Figure 7. SPI Master-Slave Interconnection
Figure 8. SPI transfer Format with CPHA = 0
*Not defined but normally MSB of character just received
0850C–MICRO–3/06
CLOCK GENERATOR
SPI
MSB
8-BIT SHIFT REGISTER
MASTER
LSB
MISO
MOSI MOSI
SCK
SS
V
The Slave Select input, SS/P1.4, is set low to select an
individual SPI device as a slave. When SS/P1.4 is set high,
the SPI port is deactivated and the MOSI/P1.5 pin can be
used as an input.
There are four combinations of SCK phase and polarity
with respect to serial data, which are determined by control
bits CPHA and CPOL. The SPI data transfer formats are
shown in Figures 8 and 9.
CC
MISO
SCK
SS
MSB
8-BIT SHIFT REGISTER
SLAVE
AT89LS8252
LSB
15