AT89LS8252-12JC Atmel, AT89LS8252-12JC Datasheet - Page 8

• Manufacturer Part Number: AT89LS8252-12JC
• Description: IC MICRO CTRL 12MHZ 44PLCC
• Manufacturer: Atmel
• Series: 89LSr

Specifications of AT89LS8252-12JC

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 32
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -
• Other names: AT89LS825212JC

Table 4. SPCR—SPI Control Register
Table 5. SPSR—SPI Status Register
8
SPCR Address = D5HReset Value = 0000 01XXB
Symbol
SPIE
SPE
DORD
MSTR
CPOL
CPHA
SPR0
SPR1
SPSR Address = AAHReset Value = 00XX XXXXB
Symbol
SPIF
WCOL
Bit
Bit
SPIE
7
SPIF
7
AT89LS8252
Function
SPI Interrupt Enable. This bit, in conjunction with the ES bit in the IE register, enables SPI interrupts: SPIE
= 1 and ES = 1 enable SPI interrupts. SPIE = 0 disables SPI interrupts.
SPI Enable. SPI = 1 enables the SPI channel and connects SS, MOSI, MISO and SCK to pins P1.4, P1.5,
P1.6, and P1.7. SPI = 0 disables the SPI channel.
Data Order. DORD = 1 selects LSB first data transmission. DORD = 0 selects MSB first data transmission.
Master/Slave Select. MSTR = 1 selects Master SPI mode. MSTR = 0 selects Slave SPI mode.
Clock Polarity. When CPOL = 1, SCK is high when idle. When CPOL = 0, SCK of the master device is low
when not transmitting. Please refer to figure on SPI Clock Phase and Polarity Control.
Clock Phase. The CPHA bit together with the CPOL bit controls the clock and data relationship between
master and slave. Please refer to figure on SPI Clock Phase and Polarity Control.
SPI Clock Rate Select. These two bits control the SCK rate of the device configured as master. SPR1 and
SPR0 have no effect on the slave. The relationship between SCK and the oscillator frequency, F
follows:
SPR1SPR0SCK = F
Function
SPI Interrupt Flag. When a serial transfer is complete, the SPIF bit is set and an interrupt is generated if
SPIE = 1 and ES = 1. The SPIF bit is cleared by reading the SPI status register with SPIF and WCOL bits
set, and then accessing the SPI data register.
Write Collision Flag. The WCOL bit is set if the SPI data register is written during a data transfer. During
data transfer, the result of reading the SPDR register may be incorrect, and writing to it has no effect. The
WCOL bit (and the SPIF bit) are cleared by reading the SPI status register with SPIF and WCOL set, and
then accessing the SPI data register.
0 0 4
0 116
1 064
1 1128
SPE
6
WCOL
6
OSC.
5
—
5
DORD
divided by
MSTR
4
—
4
CPOL
3
—
3
CPHA
2
—
2
SPR1
1
—
1
SPR0
0
—
0
0850C–MICRO–3/06
OSC.
, is as