AT89LS8252-12JC Atmel, AT89LS8252-12JC Datasheet - Page 19

• Manufacturer Part Number: AT89LS8252-12JC
• Description: IC MICRO CTRL 12MHZ 44PLCC
• Manufacturer: Atmel
• Series: 89LSr

Specifications of AT89LS8252-12JC

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 32
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -
• Other names: AT89LS825212JC

7. To verify the byte just programmed, bring pin P2.7
8. Repeat steps 3 through 7 changing the address and
9. Power-off sequence:
In the parallel programming mode, there is no auto-erase
cycle and to reprogram any non-blank byte, the user needs
to use the Chip Erase operation first to erase both arrays.
DATA Polling
The AT89LS8252 features DATA Polling to indicate the end
of a write cycle. During a write cycle in the parallel or serial
programming mode, an attempted read of the last byte writ-
ten will result in the complement of the written datum on
P0.7 (parallel mode), and on the MSB of the serial output
byte on MISO (serial mode). Once the write cycle has been
completed, true data are valid on all outputs, and the next
cycle may begin. DATA Polling may begin any time after a
write cycle has been initiated.
Ready/Busy
The progress of byte programming in the parallel program-
ming mode can also be monitored by the RDY/BSY output
signal. Pin P3.4 is pulled Low after ALE goes High during
programming to indicate BUSY. P3.4 is pulled High again
when programming is done to indicate READY.
Program Verify
If lock bits LB1 and LB2 have not been programmed, the
programmed Code or Data byte can be read back via the
address and data lines for verification. The state of the lock
bits can also be verified directly in the parallel programming
mode. In the serial programming mode, the state of the lock
bits can only be verified indirectly by observing that the lock
bit features are enabled.
Chip Erase
Both Flash and EEPROM arrays are erased electrically at
the same time. In the parallel programming mode, chip
erase is initiated by using the proper combination of control
signals and by holding ALE/PROG low for 10 ms. The
Code and Data arrays are written with all “1”s in the Chip
Erase operation.
In the serial programming mode, a chip erase operation is
initiated by issuing the Chip Erase instruction. In this mode,
chip erase is self-timed and takes about 16 ms.
During chip erase, a serial read from any address location
will return 00H at the data outputs.
0850C–MICRO–3/06
to “L” and read the programmed data at pins P0.0 to
P0.7.
data for the entire 2K or 8K bytes array or until the
end of the object file is reached.
Set XTAL1 to “L”.
Set RST and EA pins to “L”.
Turn V
CC
power off.
Serial Programming Fuse
A programmable fuse is available to disable Serial Pro-
gramming if the user needs maximum system security. The
Serial Programming Fuse can only be programmed or
erased in the Parallel Programming Mode.
The AT89LS8252 is shipped with the Serial Programming
Mode enabled.
Reading the Signature Bytes: The signature bytes are
read by the same procedure as a normal verification of
locations 030H and 031H, except that P3.6 and P3.7 must
be pulled to a logic low. The values returned are as follows:
Programming Interface
Every code byte in the Flash and EEPROM arrays can be
written, and the entire array can be erased, by using the
appropriate combination of control signals. The write oper-
ation cycle is self-timed and once initiated, will automati-
cally time itself to completion.
All major programming vendors offer worldwide support for
the Atmel microcontroller series. Please contact your local
programming vendor for the appropriate software revision.
Serial Downloading
Both the Code and Data memory arrays can be pro-
grammed using the serial SPI bus while RST is pulled to
V
and MISO (output). After RST is set high, the Programming
Enable instruction needs to be executed first before pro-
gram/erase operations can be executed.
An auto-erase cycle is built into the self-timed programming
operation (in the serial mode ONLY) and there is no need
to first execute the Chip Erase instruction unless any of the
lock bits have been programmed. The Chip Erase opera-
tion turns the content of every memory location in both the
Code and Data arrays into FFH.
The Code and Data memory arrays have separate address
spaces:
0000H to 1FFFH for Code memory and 000H to 7FFH for
Data memory.
Either an external system clock is supplied at pin XTAL1 or
a crystal needs to be connected across pins XTAL1 and
XTAL2. The maximum serial clock (SCK) frequency should
be less than 1/40 of the crystal frequency. With a 12 MHz
oscillator clock, the maximum SCK frequency is 300 kHz.
CC
. The serial interface consists of pins SCK, MOSI (input)
(030H) = 1EH indicates manufactured by Atmel
(031H) = 82H indicates 89LS8252
AT89LS8252
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