ATMEGA323L-4AI Atmel, ATMEGA323L-4AI Datasheet - Page 76
![IC AVR MCU 32K LV 4MZ IND 44TQFP](/photos/6/70/67042/313-44-tqfp_sml.jpg)
ATMEGA323L-4AI
Manufacturer Part Number
ATMEGA323L-4AI
Description
IC AVR MCU 32K LV 4MZ IND 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA323L-4PC.pdf
(247 pages)
Specifications of ATMEGA323L-4AI
Core Processor
AVR
Core Size
8-Bit
Speed
4MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
ATMEGA323L4AI
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Clock Generation
Internal Clock Generation –
The Baud Rate Generator
76
ATmega323(L)
The Clock Generation Logic generates the base clock for the Transmitter and Receiver.
The USART supports four modes of clock operation: Normal asynchronous, Double
Speed asynchronous, Master synchronous and Slave synchronous mode. The UMSEL
bit in USART Control and Status Register C (UCSRC) selects between asynchronous
and synchronous operation. Double Speed (asynchronous mode only) is controlled by
the U2X found in the UCSRA Register. When using synchronous mode (UMSEL = 1),
the Data Direction Register for the XCK pin (DDR_XCK) controls whether the clock
source is internal (Master mode) or external (Slave mode). The XCK pin is only active
when using synchronous mode.
Figure 46 shows a block diagram of the clock generation logic.
Figure 46. Clock Generation Logic, Block Diagram
Signal description:
Internal clock generation is used for the asynchronous and the synchronous Master
modes of operation. The description in this section refers to Figure 46.
The USART Baud Rate Register (UBRR) and the down-counter connected to it function
as a programmable prescaler or baud rate generator. The down-counter, running at sys-
tem clock (fosc), is loaded with the UBRR value each time the counter has counted
down to zero or when the UBRRL Register is written. A clock is generated each time the
count er re aches zero. Thi s clock is t he b aud rate generat or clock o utput
(= fosc/(UBRR+1)). The Transmitter divides the baud rate generator clock output by 2,
8, or 16 depending on mode. The baud rate generator output is used directly by the
Receiver’s clock and data recovery units. However, the recovery units use a state
machine that uses 2, 8, or 16 states depending on mode set by the state of the UMSEL,
U2X and DDR_XCK bits.
DDR_XCK
txclk
rxclk
xcki
xcko
fosc
XCK
Pin
xcki
Transmitter clock. (Internal Signal)
Receiver base clock. (Internal Signal)
Input from XCK pin (internal Signal). Used for Synchronous Slave operation.
Clock output to XCK pin (Internal Signal). Used for
synchronous Master operation.
XTAL pin frequency (System Clock).
xcko
OSC
Down-Counter
Prescaling
Register
UBRR
Sync
UBRR+1
fosc
Detector
UCPOL
Edge
/ 2
/ 4
/ 2
DDR_XCK
U2X
0
1
0
1
1457G–AVR–09/03
0
1
1
0
UMSEL
txclk
rxclk
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