ATMEGA8535L-8JI Atmel, ATMEGA8535L-8JI Datasheet - Page 142
![IC AVR MCU 8K LV 8MHZ IND 44PLCC](/photos/6/70/67043/453-44-plcc_sml.jpg)
ATMEGA8535L-8JI
Manufacturer Part Number
ATMEGA8535L-8JI
Description
IC AVR MCU 8K LV 8MHZ IND 44PLCC
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA8535L-8JI
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA8535L-8JI
Manufacturer:
TI
Quantity:
5 000
Part Number:
ATMEGA8535L-8JI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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ATmega8535(L)
be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to
re-enable SPI Master mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero,
SCK is low when idle. Refer to Figure 67 and Figure 68 for an example. The CPOL func-
tionality is summarized below:
Table 57. CPOL Functionality
• Bit 2 – CPHA: Clock Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading
(first) or trailing (last) edge of SCK. Refer to Figure 67 and Figure 68 for an example.
The CPOL functionality is summarized below:
Table 58. CPHA Functionality
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a Master. SPR1 and
SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator
Clock frequency f
Table 59. Relationship between SCK and the Oscillator Frequency
SPI2X
CPOL
CPHA
0
0
0
0
1
1
1
1
0
1
0
1
osc
is shown in the following table:
SPR1
0
0
1
1
0
0
1
1
Leading Edge
Leading Edge
Sample
Falling
Rising
Setup
SPR0
0
1
0
1
0
1
0
1
SCK Frequency
f
f
f
f
f
f
f
f
osc
osc
osc
osc
osc
osc
osc
osc
/
/
/
/
/
/
/
/
4
16
64
128
2
8
32
64
Trailing Edge
Trailing Edge
Sample
Falling
Rising
Setup
2502K–AVR–10/06
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