ATMEGA8535L-8JI Atmel, ATMEGA8535L-8JI Datasheet - Page 154
![IC AVR MCU 8K LV 8MHZ IND 44PLCC](/photos/6/70/67043/453-44-plcc_sml.jpg)
ATMEGA8535L-8JI
Manufacturer Part Number
ATMEGA8535L-8JI
Description
IC AVR MCU 8K LV 8MHZ IND 44PLCC
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA8535L-8JI
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA8535L-8JI
Manufacturer:
TI
Quantity:
5 000
Part Number:
ATMEGA8535L-8JI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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Parity Generator
Disabling the Transmitter
154
ATmega8535(L)
interrupt-driven data transmission is used, the Data Register Empty interrupt routine
must either write new data to UDR in order to clear UDRE or disable the Data Register
Empty interrupt, otherwise a new interrupt will occur once the interrupt routine
terminates.
The Transmit Complete (TXC) Flag bit is set to one when the entire frame in the transmit
Shift Register has been shifted out and there are no new data currently present in the
transmit buffer. The TXC Flag bit is automatically cleared when a transmit complete
interrupt is executed, or it can be cleared by writing a one to its bit location. The TXC
Flag is useful in half-duplex communication interfaces (like the RS-485 standard), where
a transmitting application must enter receive mode and free the communication bus
immediately after completing the transmission.
When the Transmit Compete Interrupt Enable (TXCIE) bit in UCSRB is set, the USART
Transmit Complete Interrupt will be executed when the TXC Flag becomes set (pro-
vided that global interrupts are enabled). When the transmit complete interrupt is used,
the interrupt handling routine does not have to clear the TXC Flag, this is done automat-
ically when the interrupt is executed.
The parity generator calculates the parity bit for the serial frame data. When parity bit is
enabled (UPM1 = 1), the Transmitter Control Logic inserts the parity bit between the last
data bit and the first stop bit of the frame that is sent.
The disabling of the Transmitter (setting the TXEN to zero) will not become effective
until ongoing and pending transmissions are completed (i.e., when the transmit Shift
Register and Transmit Buffer Register do not contain data to be transmitted). When dis-
abled, the Transmitter will no longer override the TxD pin.
2502K–AVR–10/06
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