ATMEGA8535L-8JI Atmel, ATMEGA8535L-8JI Datasheet - Page 176
![IC AVR MCU 8K LV 8MHZ IND 44PLCC](/photos/6/70/67043/453-44-plcc_sml.jpg)
ATMEGA8535L-8JI
Manufacturer Part Number
ATMEGA8535L-8JI
Description
IC AVR MCU 8K LV 8MHZ IND 44PLCC
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA8535L-8JI
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA8535L-8JI
Manufacturer:
TI
Quantity:
5 000
Part Number:
ATMEGA8535L-8JI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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Address Packet Format
Data Packet Format
176
ATmega8535(L)
Figure 78. START, REPEATED START, and STOP Conditions
All address packets transmitted on the TWI bus are nine bits long, consisting of seven
address bits, one READ/WRITE control bit and an acknowledge bit. If the READ/WRITE
bit is set, a read operation is to be performed, otherwise a write operation should be per-
formed. When a Slave recognizes that it is being addressed, it should acknowledge by
pulling SDA low in the ninth SCL (ACK) cycle. If the addressed slave is busy, or for
some other reason can not service the master’s request, the SDA line should be left
high in the ACK clock cycle. The Master can then transmit a STOP condition, or a
REPEATED START condition to initiate a new transmission. An address packet consist-
ing of a slave address and a READ or a WRITE bit is called SLA+R or SLA+W,
respectively.
The MSB of the address byte is transmitted first. Slave addresses can freely be allo-
cated by the designer, but the address 0000 000 is reserved for a general call.
When a general call is issued, all slaves should respond by pulling the SDA line low in
the ACK cycle. A general call is used when a Master wishes to transmit the same mes-
sage to several slaves in the system. When the general call address followed by a Write
bit is transmitted on the bus, all slaves set up to acknowledge the general call will pull
the SDA line low in the ack cycle. The following data packets will then be received by all
the slaves that acknowledged the general call. Note that transmitting the general call
address followed by a Read bit is meaningless, as this would cause contention if several
slaves started transmitting different data.
All addresses of the format 1111 xxx should be reserved for future purposes.
Figure 79. Address Packet Format
All data packets transmitted on the TWI bus are nine bits long, consisting of one data
byte and an acknowledge bit. During a data transfer, the Master generates the clock and
the START and STOP conditions, while the Receiver is responsible for acknowledging
the reception. An Acknowledge (ACK) is signalled by the Receiver pulling the SDA line
low during the ninth SCL cycle. If the Receiver leaves the SDA line high, a NACK is sig-
nalled. When the Receiver has received the last byte, or for some reason cannot receive
any more bytes, it should inform the Transmitter by sending a NACK after the final byte.
The MSB of the data byte is transmitted first.
SDA
SCL
SDA
SCL
START
START
Addr MSB
1
STOP START
2
Addr LSB
7
REPEATED START
R/W
8
ACK
9
2502K–AVR–10/06
STOP
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