ATMEGA8535L-8JI Atmel, ATMEGA8535L-8JI Datasheet - Page 80
![IC AVR MCU 8K LV 8MHZ IND 44PLCC](/photos/6/70/67043/453-44-plcc_sml.jpg)
ATMEGA8535L-8JI
Manufacturer Part Number
ATMEGA8535L-8JI
Description
IC AVR MCU 8K LV 8MHZ IND 44PLCC
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA8535L-8JI
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA8535L-8JI
Manufacturer:
TI
Quantity:
5 000
Part Number:
ATMEGA8535L-8JI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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Timer/Counter Timing
Diagrams
80
ATmega8535(L)
OCR0 and TCNT0 when the counter decrements. The PWM frequency for the output
when using phase correct PWM can be calculated by the following equation:
The “N” variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0 Register represent special cases when generating a
PWM waveform output in the phase correct PWM mode. If the OCR0 is set equal to
BOTTOM, the output will be continuously low and if set equal to MAX the output will be
continuously high for non-inverted PWM mode. For inverted PWM the output will have
the opposite logic values.
AT the very start of period 2 in Figure 33 OCn has a transition from high to low even
though there is no Compare Match. The point of this transition is to guarantee symmetry
around BOTTOM. There are two cases that give a transition without Compare Match.
•
•
The Timer/Counter is a synchronous design and the timer clock (clk
shown as a clock enable signal in the following figures. The figures include information
on when interrupt flags are set. Figure 34 contains timing data for basic Timer/Counter
operation. The figure shows the count sequence close to the MAX value in all modes
other than phase correct PWM mode.
Figure 34. Timer/Counter Timing Diagram, no Prescaling
Figure 35 shows the same timing data, but with the prescaler enabled.
TCNTn
(clk
TOVn
clk
clk
I/O
OCR0 changes its value from MAX, like in Figure 33. When the OCR0 value is MAX
the OCn pin value is the same as the result of a down-counting Compare Match. To
ensure symmetry around BOTTOM the OCn value at MAX must correspond to the
result of an up-counting Compare Match.
The timer starts counting from a value higher than the one in OCR0, and for that
reason misses the Compare Match and hence the OCn change that would have
happened on the way up.
I/O
Tn
/1)
MAX - 1
f
OCnPCPWM
MAX
=
----------------- -
N 510
f
clk_I/O
⋅
BOTTOM
T0
) is therefore
2502K–AVR–10/06
BOTTOM + 1
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