PIC18LF2539T-I/SO Microchip Technology, PIC18LF2539T-I/SO Datasheet - Page 107

• Manufacturer Part Number: PIC18LF2539T-I/SO
• Description: IC MCU FLASH 12KX16 EE AD 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF2539T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 24KB (12K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1408 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1408 B
• Interface Type: I2C, SPI, AUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.2
The TMR1 register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR1 interrupt, if enabled, is generated on overflow,
which is latched in interrupt flag bit TMR1IF (PIR1<0>).
This
setting/clearing TMR1 interrupt enable bit, TMR1IE
(PIE1<0>).
11.3
Timer1 can be configured for 16-bit reads and writes
(see Figure 11-2). When the RD16 control bit
(T1CON<7>) is set, the address for TMR1H is mapped
to a buffer register for the high byte of Timer1. A read
from TMR1L will load the contents of the high byte of
Timer1 into the Timer1 high byte buffer. This provides
TABLE 11-1:
 2002 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
TMR1L
TMR1H
T1CON
Legend:
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X39 devices; always maintain these bits clear.
Name
interrupt
Timer1 Interrupt
Timer1 16-bit Read/Write Mode
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.
GIE/GIEH PEIE/GIEL
PSPIE
PSPIP
PSPIF
RD16
Bit 7
(1)
(1)
(1)
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
can
ADIE
ADIP
ADIF
Bit 6
—
be
enabled/disabled
T1CKPS1 T1CKPS0
TMR0IE
RCIE
RCIP
RCIF
Bit 5
INT0IE
Bit 4
TXIF
TXIE
TXIP
Preliminary
by
SSPIF
SSPIE
SSPIP
RBIE
Bit 3
—
the user with the ability to accurately read all 16-bits of
Timer1 without having to determine whether a read of
the high byte, followed by a read of the low byte is valid,
due to a rollover between reads.
A write to the high byte of Timer1 must also take place
through the TMR1H buffer register. Timer1 high byte is
updated with the contents of TMR1H when a write
occurs to TMR1L. This allows a user to write all 16 bits
to both the high and low bytes of Timer1 at once.
The high byte of Timer1 is not directly readable or writ-
able in this mode. All reads and writes must take place
through the Timer1 high byte buffer register. Writes to
TMR1H do not clear the Timer1 prescaler. The
prescaler is only cleared on writes to TMR1L.
T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu
TMR0IF
Bit 2
—
—
—
TMR2IF
TMR2IE
TMR2IP
INT0IF
Bit 1
TMR1IE
TMR1IP
TMR1IF
PIC18FXX39
Bit 0
RBIF
0000 000x 0000 000u
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
POR, BOR
Value on
DS30485A-page 105
Value on
RESETS
All Other