PIC18LF2539T-I/SO Microchip Technology, PIC18LF2539T-I/SO Datasheet - Page 61

• Manufacturer Part Number: PIC18LF2539T-I/SO
• Description: IC MCU FLASH 12KX16 EE AD 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF2539T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 24KB (12K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1408 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1408 B
• Interface Type: I2C, SPI, AUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

EXAMPLE 5-3:
5.5.2
Depending on the application, good programming
practice may dictate that the value written to the mem-
ory should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.
5.5.3
If a write is terminated by an unplanned event, such as
loss of power or an unexpected RESET, the memory
location just programmed should be verified and repro-
grammed if needed.The WRERR bit is set when a write
operation is interrupted by a MCLR Reset, or a WDT
Time-out Reset during normal operation. In these situ-
ations, users can check the WRERR bit and rewrite the
location.
TABLE 5-2:
 2002 Microchip Technology Inc.
TBLPTRU
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
TBLPTRL Program Memory Table Pointer High Byte (TBLPTR<7:0>)
TABLAT
INTCON
EECON2
EECON1
IPR2
PIR2
PIE2
Legend:
PROGRAM_MEMORY
Required
Sequence
Name
x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used during FLASH/EEPROM access.
Program Memory Table Latch
EEPROM Control Register2 (not a physical register)
GIE/GIEH PEIE/GIEL TMR0IE
WRITE VERIFY
UNEXPECTED TERMINATION OF
WRITE OPERATION
EEPGD
Bit 7
—
—
—
—
BSF
BCF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
DECFSZ COUNTER_HI
BRA
BCF
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
CFGS
EECON1,EEPGD
EECON1,CFGS
EECON1,WREN
INTCON,GIE
55h
EECON2
AAh
EECON2
EECON1,WR
INTCON,GIE
PROGRAM_LOOP
EECON1,WREN
Bit 6
—
—
—
—
bit 21
Bit 5
—
—
—
—
Program Memory Table Pointer Upper Byte
(TBLPTR<20:16>)
FREE
Bit 4
INTE
EEIP
EEIF
EEIE
Preliminary
; point to FLASH program memory
; access FLASH program memory
; enable write to memory
; disable interrupts
; write 55h
; write AAh
; start program (CPU stall)
; re-enable interrupts
; loop until done
; disable write to memory
WRERR
BCLIP
BCLIF
BCLIE
RBIE
Bit 3
5.5.4
To protect against spurious writes to FLASH program
memory, the write initiate sequence must also be fol-
lowed.
(Section 20.0) for more detail.
5.6
See “Special Features of the CPU” (Section 20.0) for
details on code protection of FLASH program memory.
TMR0IF
WREN
LVDIP
LVDIF
LVDIE
Bit 2
FLASH Program Operation During
Code Protection
See
TMR3IP
TMR3IF
TMR3IE
PROTECTION AGAINST SPURIOUS
WRITES
INTF
Bit 1
WR
“Special
PIC18FXX39
RBIF
Bit 0
RD
—
—
—
Features
--00 0000 --00 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 000x 0000 000u
xx-0 x000 uu-0 u000
---1 1111 ---1 1111
---0 0000 ---0 0000
---0 0000 ---0 0000
POR, BOR
Value on:
—
DS30485A-page 59
of
the
Value on
RESETS
All Other
—
CPU”