PIC18LF2539T-I/SO Microchip Technology, PIC18LF2539T-I/SO Datasheet - Page 316

• Manufacturer Part Number: PIC18LF2539T-I/SO
• Description: IC MCU FLASH 12KX16 EE AD 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF2539T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 24KB (12K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1408 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1408 B
• Interface Type: I2C, SPI, AUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18FXX39
Programming, Device Instructions ................................... 211
PSP.See Parallel Slave Port.
Pulse Width Modulation (PWM) ....................................... 123
Pulse Width Modulation. See PWM.
PUSH ............................................................................... 240
PWM
Q
Q Clock ............................................................................ 124
R
RAM. See Data Memory
RCALL .............................................................................. 241
RCSTA Register
Register File ....................................................................... 39
Registers
DS30485A-page 314
Associated Registers ............................................... 124
CCPR1H:CCPR1L Registers ................................... 123
Duty Cycle ................................................................ 124
Period ....................................................................... 123
TMR2 to PR2 Match ................................................. 123
SPEN Bit .................................................................. 165
ADCON0 (A/D Control 0) ......................................... 181
ADCON1 (A/D Control 1) ......................................... 182
CCP1CON and CCP2CON (PWM Control) ............. 123
CONFIG1H (Configuration 1 High) .......................... 196
CONFIG2H (Configuration 2 High) .......................... 197
CONFIG2L (Configuration 2 Low) ............................ 197
CONFIG4L (Configuration 4 Low) ............................ 198
CONFIG5H (Configuration 5 High) .......................... 199
CONFIG5L (Configuration 5 Low) ............................ 199
CONFIG6H (Configuration 6 High) .......................... 200
CONFIG6L (Configuration 6 Low) ............................ 200
CONFIG7H (Configuration 7 High) .......................... 201
CONFIG7L (Configuration 7 Low) ............................ 201
DEVID1 (Device ID 1) .............................................. 202
DEVID2 (Device ID 2) .............................................. 202
EECON1 (Data EEPROM Control 1) ................... 53, 62
File Summary ....................................................... 43–45
INTCON (Interrupt Control) ........................................ 71
INTCON2 (Interrupt Control 2) ................................... 72
INTCON3 (Interrupt Control 3) ................................... 73
IPR1 (Peripheral Interrupt Priority 1) .......................... 78
IPR2 (Peripheral Interrupt Priority 2) .......................... 79
LVDCON (LVD Control) ........................................... 191
PIE1 (Peripheral Interrupt Enable 1) .......................... 76
PIE2 (Peripheral Interrupt Enable 2) .......................... 77
PIR1 (Peripheral Interrupt Request 1) ........................ 74
PIR2 (Peripheral Interrupt Request 2) ........................ 75
RCON (Register Control) ........................................... 80
RCON (RESET Control) ............................................. 50
RCSTA (Receive Status and Control) ...................... 167
SSPCON1 (MSSP Control 1)
SSPCON1 (MSSP Control 1), I
SSPCON2 (MSSP Control 2), I
SSPSTAT (MSSP Status)
SSPSTAT (MSSP Status), I
STATUS ..................................................................... 49
STKPTR (Stack Pointer) ............................................ 35
T0CON (Timer0 Control) ............................................ 99
T1CON (Timer 1 Control) ......................................... 103
T2CON (Timer2 Control) .......................................... 107
T3CON (Timer3 Control) .......................................... 109
TRISE ......................................................................... 94
SPI Mode ......................................................... 127
SPI Mode ......................................................... 126
2
C Mode ....................... 135
2
2
C Mode .................. 136
C Mode .................. 137
Preliminary
RESET ................................................................23, 195, 241
RETFIE ............................................................................ 242
RETLW ............................................................................ 242
RETURN .......................................................................... 243
Return Address Stack ........................................................ 34
Revision History ............................................................... 305
RLCF ............................................................................... 243
RLNCF ............................................................................. 244
RRCF ............................................................................... 244
RRNCF ............................................................................ 245
S
SCI. See USART
SCK ................................................................................. 125
SDI ................................................................................... 125
SDO ................................................................................. 125
Serial Clock, SCK ............................................................ 125
Serial Communication Interface. See USART
Serial Data In, SDI ........................................................... 125
Serial Data Out, SDO ....................................................... 125
Serial Peripheral Interface. See SPI Mode
SETF ................................................................................ 245
Single Phase Induction Motor Control Module.
Slave Select Synchronization .......................................... 131
Slave Select, SS .............................................................. 125
SLEEP ..............................................................195, 205, 246
Software Simulator (MPLAB SIM) .................................... 254
Special Features of the CPU ........................................... 195
Special Function Registers ................................................ 39
SPI Mode
SS .................................................................................... 125
SSPOV Status Flag ......................................................... 155
TXSTA (Transmit Status and Control) ..................... 166
WDTCON (Watchdog Timer Control) ...................... 203
Brown-out Reset (BOR) ........................................... 195
MCLR Reset (During SLEEP) .................................... 23
MCLR Reset (Normal Operation) .............................. 23
Oscillator Start-up Timer (OST) ............................... 195
Power-on Reset (POR) .......................................23, 195
Power-up Timer (PWRT) ......................................... 195
Programmable Brown-out Reset (BOR) .................... 23
RESET Instruction ..................................................... 23
Stack Full Reset ......................................................... 23
Stack Underflow Reset .............................................. 23
Watchdog Timer (WDT) Reset .................................. 23
Associated Registers ................................................. 35
Pointer (STKPTR) ...................................................... 34
Top-of-Stack Access .................................................. 34
See Motor Control. ................................................... 113
Configuration Registers ....................................196–201
Map ............................................................................ 42
Associated Registers ............................................... 133
Bus Mode Compatibility ........................................... 133
Effects of a RESET .................................................. 133
Master Mode ............................................................ 130
Master/Slave Connection ......................................... 129
Overview .................................................................. 125
Serial Clock .............................................................. 125
Serial Data In ........................................................... 125
Serial Data Out ........................................................ 125
Slave Mode .............................................................. 131
Slave Select ............................................................. 125
Slave Select Synchronization .................................. 131
Slave Synch Timing ................................................. 131
SLEEP Operation .................................................... 133
SPI Clock ................................................................. 130
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