AT89C5131-S3SIL Atmel, AT89C5131-S3SIL Datasheet - Page 143
AT89C5131-S3SIL
Manufacturer Part Number
AT89C5131-S3SIL
Description
IC 8051 MCU FLASH 32K USB 52PLCC
Manufacturer
Atmel
Series
AT89C513xr
Datasheet
1.AT89C5131-S3SIL.pdf
(176 pages)
Specifications of AT89C5131-S3SIL
Core Processor
C52X2
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
LED, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
For Use With
AT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-05 - KIT STARTER FOR AT89C5131
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
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4136B–USB–09/03
Table 101. UEPINT Register
UEPINT (S:F8h read-only)
USB Endpoint Interrupt Register
Reset Value = 00h
Bit Number
7
-
7
6
5
4
3
2
1
0
Mnemonic Description
EP6INT
EP6INT
EP5INT
EP4INT
EP3INT
EP2INT
EP1INT
EP0INT
Bit
6
-
Reserved
The value read from this bit is always 0. Do not set this bit.
Endpoint 6 Interrupt
This bit is set by hardware when an interrupt is triggered by the (see Table 96 on
page 139) and this endpoint interrupt is enabled by the UEPIEN Register
UEPIEN (S:C2h) USB Endpoint Interrupt Enable Register (see Figure 102 on
page 144).
This bit is cleared by software.
Endpoint 5 Interrupt
This bit is set by hardware when an interrupt is triggered by the (see Table 96 on
page 139) and this endpoint interrupt is enabled by the UEPIEN Register
UEPIEN (S:C2h) USB Endpoint Interrupt Enable Register (see Figure 102 on
page 144).
This bit is cleared by software.
Endpoint 4 Interrupt
This bit is set by hardware when an interrupt is triggered by the (see Table 96 on
page 139) and this endpoint interrupt is enabled by the UEPIEN Register
UEPIEN (S:C2h) USB Endpoint Interrupt Enable Register (see Figure 102 on
page 144).
This bit is cleared by software.
Endpoint 3 Interrupt
This bit is set by hardware when an interrupt is triggered by the (see Table 96 on
page 139) and this endpoint interrupt is enabled by the UEPIEN Register
UEPIEN (S:C2h) USB Endpoint Interrupt Enable Register (see Figure 102 on
page 144).
This bit is cleared by software.
Endpoint 2 Interrupt
This bit is set by hardware when an interrupt is triggered by the (see Table 96 on
page 139) and this endpoint interrupt is enabled by the UEPIEN Register
UEPIEN (S:C2h) USB Endpoint Interrupt Enable Register (see Figure 102 on
page 144).
This bit is cleared by software.
Endpoint 1 Interrupt
This bit is set by hardware when an interrupt is triggered by the (see Table 96 on
page 139) and this endpoint interrupt is enabled by the UEPIEN Register
UEPIEN (S:C2h) USB Endpoint Interrupt Enable Register (see Figure 102 on
page 144).
This bit is cleared by software.
Endpoint 0 Interrupt
This bit is set by hardware when an interrupt is triggered by the (see Table 96 on
page 139) and this endpoint interrupt is enabled by the UEPIEN Register
UEPIEN (S:C2h) USB Endpoint Interrupt Enable Register (see Figure 102 on
page 144).
This bit is cleared by software.
EP5INT
5
EP4INT
4
EP3INT
3
EP2INT
2
AT89C5131
EP1INT
1
EP0INT
0
143
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