AT89C5131-S3SIL Atmel, AT89C5131-S3SIL Datasheet - Page 70

• Manufacturer Part Number: AT89C5131-S3SIL
• Description: IC 8051 MCU FLASH 32K USB 52PLCC
• Manufacturer: Atmel
• Series: AT89C513xr

Specifications of AT89C5131-S3SIL

• Core Processor: C52X2
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: LED, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• For Use With: AT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-05 - KIT STARTER FOR AT89C5131
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -

70
AT89C5131
Table 57. SCON Register – SCON Serial Control Register (98h)
Reset Value = 0000 0000b
Bit addressable
Number
FE/SM0
Bit
7
6
5
4
3
2
1
0
7
Mnemonic
SM0
SM1
SM2
REN
RB8
Bit
TB8
FE
SM1
RI
TI
6
Description
Framing Error bit (SMOD0 = 1)
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
SMOD0 must be set to enable access to the FE bit
Serial port Mode bit 0
Refer to SM1 for serial port mode selection.
SMOD0 must be cleared to enable access to the SM0 bit
Serial port Mode bit 1
SM0 SM1 Mode
0
0
1
1
Serial port Mode 2 bit/Multiprocessor Communication Enable bit
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3, and
eventually mode 1. This bit should be cleared in mode 0.
Reception Enable bit
Clear to disable serial reception.
Set to enable serial reception.
Transmitter Bit 8/Ninth bit to Transmit in Modes 2 and 3
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
Receiver Bit 8/Ninth bit received in modes 2 and 3
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.
Transmit Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the
stop bit in the other modes.
Receive Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 32. and
Figure 33. in the other modes.
SM2
0
1
0
1
5
0
1
2
3
REN
4
Description
Shift Register
8-bit UART
9-bit UART
9-bit UART
TB8
3
Baud Rate
F
Variable
F
Variable
CPU PERIPH
CPU PERIPH/
RB8
2
/6
32 or/16
TI
1
4136B–USB–09/03
RI
0