AT89C5131-S3SIL Atmel, AT89C5131-S3SIL Datasheet - Page 20
![IC 8051 MCU FLASH 32K USB 52PLCC](/photos/12/13/121324/453-52-plcc_sml.jpg)
AT89C5131-S3SIL
Manufacturer Part Number
AT89C5131-S3SIL
Description
IC 8051 MCU FLASH 32K USB 52PLCC
Manufacturer
Atmel
Series
AT89C513xr
Datasheet
1.AT89C5131-S3SIL.pdf
(176 pages)
Specifications of AT89C5131-S3SIL
Core Processor
C52X2
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
LED, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
For Use With
AT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-05 - KIT STARTER FOR AT89C5131
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
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PLL
PLL Description
Figure 7. PLL Block Diagram and Symbol
20
AT89C5131
CLOCK
OSC
N divider
N3:0
Figure 6. Crystal Connection
The AT89C5131 PLL is used to generate internal high frequency clock (the USB Clock)
synchronized with an external low-frequency (the Peripheral Clock). The PLL clock is
used to generate the USB interface clock. Figure 7 shows the internal structure of the
PLL.
The PFLD block is the Phase Frequency Comparator and Lock Detector. This block
makes the comparison between the reference clock coming from the N divider and the
reverse clock coming from the R divider and generates some pulses on the Up or Down
signal depending on the edge position of the reverse clock. The PLLEN bit in PLLCON
register is used to enable the clock generation. When the PLL is locked, the bit PLOCK
in PLLCON register (see Figure 7) is set.
The CHP block is the Charge Pump that generates the voltage reference for the VCO by
injecting or extracting charges from the external filter connected on PLLF pin (see
Fi gure 8) . Value of the filter components ar e detailed in the Section “ DC
Characteristics”.
The VCO block is the Voltage Controlled Oscillator controlled by the voltage V
duced by the charge pump. It generates a square wave signal: the PLL clock.
Figure 8. PLL Filter Connection
The typical values are: R = 100
PLLCON.1
PLLCON.0
PLOCK
PLLEN
USBclk
PFLD
Down
=
Up
OSCclk
---------------------------------------------- -
R divider
R3:0
PFILT
PFILT
CHP
N
VSS
+
1
, C1 = 10 nf, C2 = 2.2 nF.
R
+
Vref
C1
C2
1
VSS
R
VCO
C1
Q
VSS
X1
X2
C2
USB Clock Symbol
USB Clock
CLOCK
USB
4136B–USB–09/03
REF
pro-
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