AT89C5131-S3SIL Atmel, AT89C5131-S3SIL Datasheet - Page 96
AT89C5131-S3SIL
Manufacturer Part Number
AT89C5131-S3SIL
Description
IC 8051 MCU FLASH 32K USB 52PLCC
Manufacturer
Atmel
Series
AT89C513xr
Datasheet
1.AT89C5131-S3SIL.pdf
(176 pages)
Specifications of AT89C5131-S3SIL
Core Processor
C52X2
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
LED, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
For Use With
AT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-05 - KIT STARTER FOR AT89C5131
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
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Serial Peripheral Status Register
(SPSTA)
96
AT89C5131
Reset Value = 0001 0100b
Not bit addressable
The Serial Peripheral Status Register contains flags to signal the following conditions:
•
•
•
Table 76 describes the SPSTA register and explains the use of every bit in the register.
Table 76. SPSTA Register
SPSTA - Serial Peripheral Status and Control register (0C4H)
Number
Number
Bit
SPIF
Data transfer complete
Write collision
Inconsistent logic level on SS pin (mode fault error)
Bit
2
1
7
7
6
5
4
3
Bit Mnemonic Description
Mnemonic Description
SSERR
WCOL
WCOL
MODF
SPR1
SPR0
SPIF
Bit
6
-
Serial Peripheral data transfer flag
Cleared by hardware to indicate data transfer is in progress or has been
approved by a clearing sequence.
Set by hardware to indicate that the data transfer has been completed.
Write Collision flag
Cleared by hardware to indicate that no collision has occurred or has been
approved by a clearing sequence.
Set by hardware to indicate that a collision has been detected.
Synchronous Serial Slave Error flag
Set by hardware when SS is de-
asserted before the end of a received data.
Cleared by disabling the SPI (clearing SPEN bit in SPCON).
Mode Fault
Cleared by hardware to indicate that the SS pin is at appropriate logic level, or
has been approved by a clearing sequence.
Set by hardware to indicate that the SS pin is at inappropriate logic level.
Reserved
The value read from this bit is indeterminate. Do not set this bit
SPR2
0
0
0
0
1
1
1
1
SSERR
5
0
0
1
1
0
0
1
1
SPR1
MODF
4
0
1
0
1
0
1
0
1
SPR0
Serial Peripheral Rate
Invalid
F
F
F
F
F
F
Invalid
CLK PERIPH/
CLK PERIPH/
CLK PERIPH/
CLK PERIPH/
CLK PERIPH/
CLK PERIPH/
3
-
4
8
16
32
64
128
2
-
1
-
4136B–USB–09/03
0
-
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