AT89C5131-S3SIL Atmel, AT89C5131-S3SIL Datasheet - Page 76

• Manufacturer Part Number: AT89C5131-S3SIL
• Description: IC 8051 MCU FLASH 32K USB 52PLCC
• Manufacturer: Atmel
• Series: AT89C513xr

Specifications of AT89C5131-S3SIL

• Core Processor: C52X2
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: LED, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• For Use With: AT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-05 - KIT STARTER FOR AT89C5131
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -

Registers
76
AT89C5131
Each of the interrupt sources can be individually enabled or disabled by setting or clear-
ing a bit in the Interrupt Enable register (Table 62). This register also contains a global
disable bit, which must be cleared to disable all interrupts at once.
Each interrupt source can also be individually programmed to one out of four priority lev-
els by setting or clearing a bit in the Interrupt Priority register (Table 63.) and in the
Interrupt Priority High register (Table 64). Table 61. shows the bit values and priority lev-
els associated with each combination.
The PCA interrupt vector is located at address 0033H, the SPI interrupt vector is located
at address 0043H and Keyboard interrupt vector is located at address 004BH. All other
vectors addresses are the same as standard C52 devices.
Table 61. Priority Level Bit Values
A low-priority interrupt can be interrupted by a high priority interrupt, but not by another
low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt
source.
If two interrupt requests of different priority levels are received simultaneously, the
request of higher priority level is serviced. If interrupt requests of the same priority level
are received simultaneously, an internal polling sequence determines which request is
serviced. Thus within each priority level there is a second priority structure determined
by the polling sequence.
IPH.x
0
0
1
1
IPL.x
0
1
0
1
Interrupt Level Priority
3 (Highest)
0 (Lowest)
1
2
4136B–USB–09/03