ST92F250CV2TB STMicroelectronics, ST92F250CV2TB Datasheet - Page 422

• Manufacturer Part Number: ST92F250CV2TB
• Description: IC MCU 256K FLASH 100-TQFP
• Manufacturer: STMicroelectronics
• Series: ST9r

Specifications of ST92F250CV2TB

• Core Processor: ST9
• Core Size: 8/16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: ST92F25x
• Core: ST9
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST92F150-EPB
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit x 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2140

ST92F124/F150/F250 - KNOWN LIMITATIONS
KNOWN LIMITATIONS (Cont’d)
Here is an example of a patch for the MFT1 using
DMA in ouput compare mode, inserted at the be-
ginning of the MFT0 interrupt routine:
spp #8 ;Set to page 8 (mft1)
tm T_IDMR,#0x08 ;test mft0 OCMP dma
mask bit
jxnz MFT0_it_routine
cpw DMA_CNT1,#0 ;If the DMA count is
not at zero the block did not complete
jxeq MFT0_it_routine
and T_FLAGR,#11011111b ;Clear dma
compare interrupt request
422/429
1
or T_IDMR,#0x08 ;Re-enable the com-
pare 0 dma
MFT0_it_routine: ;MFT0 interrupt rou-
tine code
In addition, the peripheral DMA priorities must be
organized so that the MFT DMA priorities are the
highest. This way the impact is limited: DMA re-
quests with the wrong Mask Bit Reset are serv-
iced.
Workaround Limitation
If the counter event period is too short, the failure
recovery in the interrupt routines will not work.