Z8F3201VN020EC00TR Zilog, Z8F3201VN020EC00TR Datasheet - Page 82

• Manufacturer Part Number: Z8F3201VN020EC00TR
• Description: IC ENCORE MCU FLASH 32K 44PLCC
• Manufacturer: Zilog
• Series: Encore!®r

Specifications of Z8F3201VN020EC00TR

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 44-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: Z8F3201VN020EC00T

PS017610-0404
If the Timer reaches
The steps for configuring a timer for Compare mode and initiating the count are as fol-
lows:
1. Write to the Timer Control register to:
2. Write to the Timer High and Low Byte registers to set the starting count value.
3. Write to the Timer Reload High and Low Byte registers to set the Compare value.
4. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
5. If using the Timer Output function, configure the associated GPIO port pin for the
6. Write to the Timer Control register to enable the timer and initiate counting.
In Compare mode, the system clock always provides the timer input. The Compare time is
given by the following equation:
Gated Mode
In Gated mode, the timer counts only when the Timer Input signal is in its active state
(asserted), as determined by the TPOL bit in the Timer Control register. When the Timer
Input signal is asserted, counting begins. A timer interrupt is generated when the Timer
Input signal is deasserted or a timer reload occurs. To determine if a Timer Input signal
deassertion generated the interrupt, read the associated GPIO input value and compare to
the value stored in the TPOL bit.
The timer counts up to the 16-bit Reload value stored in the Timer Reload High and Low
Byte registers. The timer input is the system clock. When reaching the Reload value, the
timer generates an interrupt, the count value in the Timer High and Low Byte registers is
reset to
Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state
(from Low to High or from High to Low) at timer reset.
The steps for configuring a timer for Gated mode and initiating the count are as follows:
1. Write to the Timer Control register to:
Compare Mode Time (s)
–
–
–
–
the relevant interrupt registers.
Timer Output alternate function.
–
0001H
Disable the timer
Configure the timer for Compare mode.
Set the prescale value.
Set the initial logic level (High or Low) for the Timer Output alternate function, if
desired.
Disable the timer
and counting resumes (assuming the Timer Input signal is still asserted).
FFFFH
, the timer rolls over to
=
(
----------------------------------------------------------------------------------------------------------- -
Compare Value Start Value
System Clock Frequency (Hz)
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
–
0000H
and continue counting.
) Prescale
×
Z8 Encore!
Timers
®
64