MC68HC705B16CFN Freescale Semiconductor, MC68HC705B16CFN Datasheet - Page 80

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MC68HC705B16CFN

Manufacturer Part Number
MC68HC705B16CFN
Description
IC MCU 2.1MHZ 15K OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC68HC705B16CFN

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SCI
Peripherals
POR, WDT
Number Of I /o
32
Program Memory Size
15KB (15K x 8)
Program Memory Type
OTP
Eeprom Size
256 x 8
Ram Size
352 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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6
If the receiver detects that a break (RDRF = 1, FE = 1, receiver data register = $0000) produced
the framing error, the start bit will not be artificially induced and the receiver must actually detect
a logic one before the start bit can be recognised (see
6.9
Transmit data is the serial data from the internal data bus that is applied through the SCI to the
output line. Data format is as discussed in
generates a bit time by using a derivative of the RT clock, thus producing a transmission rate equal
to 1/16th that of the receiver sample clock (assuming the same baud rate is selected for both the
receiver and transmitter).
Freescale
6-8
Expected stop
RDI
Break
Transmit data out (TDO)
RDI
RDI
Data
Data
Figure 6-6 Artificial start following a framing error
SERIAL COMMUNICATIONS INTERFACE
Figure 6-7 SCI start bit following a break
Data samples
Data samples
Data samples
Expected stop
Expected stop
b) Case 2: receive line high during expected start edge
a) Case 1: receive line low during artificial edge
Section 6.5
Start edge
Figure
Artificial edge
and shown in
qualifiers
Start
6-7).
verification
Start edge
samples
Detected as valid start edge
Start bit
Figure
Start bit
Start bit
6-3. The transmitter
Data
Data
MC68HC05B6
Rev. 4.1

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