MC68HC705C9ACFB Freescale Semiconductor, MC68HC705C9ACFB Datasheet - Page 35

• Manufacturer Part Number: MC68HC705C9ACFB
• Description: IC MCU 16K 2.1MHZ OTP 44-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705C9ACFB

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 352 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

Chapter 4
Interrupts
4.1 Introduction
The MCU can be interrupted by five different sources, four maskable hardware interrupts, and one
non-maskable software interrupt:
Interrupts cause the processor to save register contents on the stack and to set the interrupt mask (I bit)
to prevent additional interrupts. The RTI instruction causes the register contents to be recovered from the
stack and normal processing to resume.
Unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but are
considered pending until the current instruction is complete.
When the current instruction is complete, the processor checks all pending hardware interrupts. If
interrupts are not masked (CCR I bit clear) and if the corresponding interrupt enable bit is set, the
processor proceeds with interrupt processing; otherwise, the next instruction is fetched and executed.
If an external interrupt and a timer, SCI, or SPI interrupt are pending at the end of an instruction execution,
the external interrupt is serviced first. The SWI is executed the same as any other instruction, regardless
of the I-bit state.
Table 4-1
processing flow.
4.2 Non-Maskable Software Interrupt (SWI)
The SWI is an executable instruction and a non-maskable interrupt: It is executed regardless of the state
of the I bit in the CCR. If the I bit is zero (interrupts enabled), SWI executes after interrupts which were
pending when the SWI was fetched, but before interrupts generated after the SWI was fetched. The
interrupt service routine address is specified by the contents of memory locations $3FFC and $3FFD.
Freescale Semiconductor
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External signal on the IRQ pin or port B pins
16-bit programmable timer
Serial communications interface
Serial peripheral interface
Software interrupt instruction (SWI)
shows the relative priority of all the possible interrupt sources.
The current instruction is the one already fetched and being operated on.
MC68HC05C9A Advance Information Data Sheet, Rev. 4.1
NOTE
Figure 4-1
shows the interrupt
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