MC68HC705C9ACFB Freescale Semiconductor, MC68HC705C9ACFB Datasheet - Page 36
![no-image](/images/manufacturer_photos/0/2/262/freescale_semiconductor_sml.jpg)
MC68HC705C9ACFB
Manufacturer Part Number
MC68HC705C9ACFB
Description
IC MCU 16K 2.1MHZ OTP 44-QFP
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet
1.MC705C9ACPE.pdf
(118 pages)
Specifications of MC68HC705C9ACFB
Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
24
Program Memory Size
16KB (16K x 8)
Program Memory Type
OTP
Ram Size
352 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HC705C9ACFB
Manufacturer:
FREESCALE
Quantity:
164
Company:
Part Number:
MC68HC705C9ACFB
Manufacturer:
MOTOROLA
Quantity:
2 161
Company:
Part Number:
MC68HC705C9ACFB
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68HC705C9ACFB
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
Company:
Part Number:
MC68HC705C9ACFBE
Manufacturer:
FREESCALE
Quantity:
1 827
Company:
Part Number:
MC68HC705C9ACFBE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Interrupts
4.3 External Interrupt (IRQ or Port B)
If the interrupt mask bit (I bit) of the CCR is set, all maskable interrupts (internal and external) are disabled.
Clearing the I bit enables interrupts. The interrupt request is latched immediately following the falling edge
of IRQ. It is then synchronized internally and serviced as specified by the contents of $3FFA and $3FFB.
When any of the port B pullups are enabled, each pin becomes an additional external interrupt source
which is executed identically to the IRQ pin. Port B interrupts follow the same edge/edge-level selection
as the IRQ pin. The branch instructions BIL and BIH also respond to the port B interrupts in the same way
as the IRQ pin. See
Either a level-sensitive and edge-sensitive trigger or an edge-sensitive-only trigger operation is
selectable. In MC68HC05C9A mode, the sensitivity is software controlled by the IRQ bit in the C9A option
register ($3FDF). In the MC68HC05C12A mode, the sensitivity is determined by the C12IRQ bit in the
C12 mask option register ($3FF1).
36
Function
interrupts
interrupts
interrupts
Software
interrupt
External
interrupt
Reset
(SWI)
Timer
SCI
SPI
The internal interrupt latch is cleared in the first part of the interrupt service
routine; therefore, one external interrupt pulse can be latched and serviced
as soon as the I bit is cleared.
7.3 Port
IRQ pin port B pins
Table 4-1. Vector Addresses for Interrupts and Resets
Power-on reset
COP watchdog
RESET pin
User code
MODF bit
RDRF bit
TDRE bit
IDLE bit
SPIF bit
MC68HC05C9A Advance Information Data Sheet, Rev. 4.1
OCF bit
Source
TOF bit
ICF bit
OR bit
TC bit
B.
Local Mask
OCIE bit
TOIE bit
TCIE bit
ICIE bit
ILIE bit
RIE bit
None
None
None
SPIE
NOTE
Global Mask
None
None
I bit
I bit
I bit
I bit
(1 = Highest)
Same priority
as instruction
Priority
1
2
3
4
5
Freescale Semiconductor
$3FFC–$3FFD
$3FFE–$3FFF
$3FFA–$3FFB
$3FF8–$3FF9
$3FF6–$3FF7
$3FF4–$3FF5
Address
Vector