MC68HC705C9ACFB Freescale Semiconductor, MC68HC705C9ACFB Datasheet - Page 63

• Manufacturer Part Number: MC68HC705C9ACFB
• Description: IC MCU 16K 2.1MHZ OTP 44-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705C9ACFB

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 352 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

9.9 Address Mark Wakeup
In address mark wakeup, the most significant bit (MSB) in a character is used to indicate whether it is an
address (logic 1) or data (logic 0) character. Sleeping receivers will wake up whenever an address
character is received. Systems using this method for wakeup would set the MSB of the first character of
each message and leave it clear for all other characters in the message. Idle periods may be present
within messages and no idle time is required between messages for this wakeup method.
9.10 Receive Data In (RDI)
Receive data is the serial data that is applied through the input line and the SCI to the internal bus. The
receiver circuitry clocks the input at a rate equal to 16 times the baud rate. This time is referred to as the
RT rate in
The receiver clock generator is controlled by the baud rate register; however, the SCI is synchronized by
the start bit, independent of the transmitter.
Once a valid start bit is detected, the start bit, each data bit, and the stop bit are sampled three times at
RT intervals 8 RT, 9 RT, and 10 RT
(1 RT is the position where the bit is expected to start), as shown in
determined by voting logic which takes the value of the majority of the samples. A noise flag is set when
all three samples on a valid start bit or data bit or the stop bit do not agree.
Freescale Semiconductor
16X INTERNAL SAMPLING CLOCK
RT CLOCK EDGES FOR ALL THREE EXAMPLES
IDLE
RDI
RDI
RDI
Figure 9-4
1
1
1
RDI
Figure 9-4. SCI Examples of Start Bit Sampling Techniques
1
1
1
PREVIOUS BIT
Figure 9-5. SCI Sampling Technique Used on All Bits
and as the receiver clock in
16RT 1RT
1
1
1
MC68HC05C9A Advance Information Data Sheet, Rev. 4.1
NOISE
1
1
0
1
1
1
1
1
1
8RT
1
1
1
Figure
SAMPLES
9RT
1
1
1
START
START
START
9-6.
0
0
10RT
0
1RT
2RT
3RT
0
0
Figure
0
16RT 1RT
4RT
NOISE
9-5. The value of the bit is
NEXT BIT
0
1
0
5RT
Address Mark Wakeup
6RT
7RT
0
0
0
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