MC68HC705C9ACFB Freescale Semiconductor, MC68HC705C9ACFB Datasheet - Page 68
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MC68HC705C9ACFB
Manufacturer Part Number
MC68HC705C9ACFB
Description
IC MCU 16K 2.1MHZ OTP 44-QFP
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet
1.MC705C9ACPE.pdf
(118 pages)
Specifications of MC68HC705C9ACFB
Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
24
Program Memory Size
16KB (16K x 8)
Program Memory Type
OTP
Ram Size
352 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
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Serial Communications Interface (SCI)
TDRE — Transmit Data Register Empty Flag
TC — Transmission Complete Flag
RDRF — Receive Data Register Full Flag
IDLE — Receiver Idle Flag
OR — Receiver Overrun Flag
NF — Receiver Noise Flag
68
This clearable, read-only flag is set when the data in the SCDR transfers to the transmit shift register.
TDRE generates an interrupt request if the TIE bit in SCCR2 is also set. Clear the TDRE bit by reading
the SCSR with TDRE set and then writing to the SCDR. Reset sets the TDRE bit. Software must
initialize the TDRE bit to logic 0 to avoid an instant interrupt request when turning the transmitter on.
This clearable, read-only flag is set when the TDRE bit is set, and no data, preamble, or break
character is being transmitted. TDRE generates an interrupt request if the TCIE bit in SCCR2 is also
set. Clear the TC bit by reading the SCSR with TC set, and then writing to the SCDR. Reset sets the
TC bit. Software must initialize the TC bit to logic 0 to avoid an instant interrupt request when turning
the transmitter on.
This clearable, read-only flag is set when the data in the receive shift register transfers to the SCI data
register. RDRF generates an interrupt request if the RIE bit in the SCCR2 is also set. Clear the RDRF
bit by reading the SCSR with RDRF set and then reading the SCDR.
This clearable, read-only flag is set when 10 or 11 consecutive logic 1s appear on the receiver input.
IDLE generates an interrupt request if the ILIE bit in the SCCR2 is also set. Clear the ILIE bit by reading
the SCSR with IDLE set and then reading the SCDR.
This clearable, read-only flag is set if the SCDR is not read before the receive shift register receives
the next word. OR generates an interrupt request if the RIE bit in the SCCR2 is also set. The data in
the shift register is lost, but the data already in the SCDR is not affected. Clear the OR bit by reading
the SCSR with OR set and then reading the SCDR.
This clearable, read-only flag is set when noise is detected in data received in the SCI data register.
Clear the NF bit by reading the SCSR and then reading the SCDR.
1 = SCDR data transferred to transmit shift register
0 = SCDR data not transferred to transmit shift register
1 = No transmission in progress
0 = Transmission in progress
1 = Received data available in SCDR
0 = Received data not available in SCDR
1 = Receiver input idle
0 = Receiver input not idle
1 = Receive shift register full and RDRF = 1
0 = No receiver overrun
1 = Noise detected in SCDR
0 = No noise detected in SCDR
Reset:
$0010
Read:
Write:
TDRE
Bit 7
1
MC68HC05C9A Advance Information Data Sheet, Rev. 4.1
= Unimplemented
Figure 9-11. SCI Status Register (SCSR)
TC
6
1
RDRF
5
0
IDLE
4
0
OR
3
0
NF
2
0
FE
1
0
Freescale Semiconductor
Bit 0
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