C8051F022 Silicon Laboratories Inc, C8051F022 Datasheet - Page 183
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C8051F022
Manufacturer Part Number
C8051F022
Description
IC 8051 MCU 64K FLASH 100TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F02xr
Specifications of C8051F022
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
64
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x10b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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18.
The SMBus0 I/O interface is a two-wire, bi-directional serial bus. SMBus0 is compliant with the System Manage-
ment Bus Specification, version 1.1, and compatible with the I
system controller are byte oriented with the SMBus0 interface autonomously controlling the serial transfer of the
data. Data can be transferred at up to 1/8th of the system clock if desired (this can be faster than allowed by the
SMBus specification, depending on the system clock used). A method of extending the clock-low duration is avail-
able to accommodate devices with different speed capabilities on the same bus.
SMBus0 may operate as a master and/or slave, and may function on a bus with multiple masters. SMBus0 provides
control of SDA (serial data), SCL (serial clock) generation and synchronization, arbitration logic, and START/STOP
control and generation. SMBus0 is controlled by SFRs as described in
SMBUS
IRQ
SYSTEM MANAGEMENT BUS / I
S
L
V
6
S
L
V
5
SMB0ADR
S
L
V
4
B
U
S
Y
Interrupt
Request
B
S
L
V
3
M
E
N
S
B
7
S
L
V
2
SMB0CN
S
T
A
A
S
L
V
1
O
S
T
S
L
V
0
S
I
G
C
A
A
F
T
E
B
O
T
E
SFR Bus
0000000b
SMBUS CONTROL LOGIC
Arbitration
SCL Synchronization
Status Generation
SCL Generation (Master Mode)
IRQ Generation
A
7 MSBs
S
A
T
7
S
A
SFR Bus
T
6
SMB0STA
S
T
A
Figure 18.1. SMBus0 Block Diagram
5
S
T
A
4
8
S
T
A
3
SMB0DAT
S
T
A
2
Read
S
T
A
1
7
S
T
A
0
6
8
SMB0DAT
5
4
C
R
7
3
C
R
6
Clock Divide
Data Path
8
Control
2
SMB0CR
C
R
5
Logic
1
SMB0DAT
C
R
4
Write to
0
C
R
3
C
R
2
Rev. 1.4
C
R
1
Control
C
R
0
SDA
2
2
Control
C BUS (SMBUS0)
C serial bus. Reads and writes to the interface by the
SCL
1
0
SYSCLK
Section 18.4 on page
FILTER
FILTER
N
N
C8051F020/1/2/3
SDA
SCL
C
R
O
R
S
S
B
A
189.
Port I/O
183