C8051F022 Silicon Laboratories Inc, C8051F022 Datasheet - Page 203
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C8051F022
Manufacturer Part Number
C8051F022
Description
IC 8051 MCU 64K FLASH 100TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F02xr
Specifications of C8051F022
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
64
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x10b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F022
Manufacturer:
SILICON
Quantity:
513
Company:
Part Number:
C8051F022
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F022-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Part Number:
C8051F022-GQ
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Company:
Part Number:
C8051F022-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F022R
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Bits7-0:
Bits7-0:
SCR7
R/W
R/W
Bit7
Bit7
SCR7-SCR0: SPI0 Clock Rate
These bits determine the frequency of the SCK output when the SPI0 module is configured for master
mode operation. The SCK clock frequency is a divided down version of the system clock, and is
given in the following equation, where SYSCLK is the system clock frequency and SPI0CR is the 8-
bit value held in the SPI0CR register.
f
for 0 <= SPI0CKR <= 255
Example: If SYSCLK = 2 MHz and SPI0CKR = 0x04,
f
f
SPI0DAT: SPI0 Transmit and Receive Data.
The SPI0DAT register is used to transmit and receive SPI0 data. Writing data to SPI0DAT places the
data immediately into the shift register and initiates a transfer when in Master Mode. A read of
SPI0DAT returns the contents of the receive buffer.
SCK
SCK
SCK
SCR6
R/W
R/W
Bit6
Bit6
=
=
=
------------------------------------------------ -
2
------------------------- -
2
200kHz
2000000
Figure 19.7. SPI0CKR: SPI0 Clock Rate Register
SPI0CKR
4
SYSCLK
SCR5
Figure 19.8. SPI0DAT: SPI0 Data Register
R/W
R/W
Bit5
+
Bit5
1
+
SCR4
R/W
R/W
Bit4
Bit4
1
SCR3
R/W
R/W
Bit3
Bit3
Rev. 1.4
SCR2
R/W
R/W
Bit2
Bit2
SCR1
C8051F020/1/2/3
R/W
R/W
Bit1
Bit1
SCR0
R/W
R/W
Bit0
Bit0
SFR Address:
SFR Address:
00000000
00000000
Reset Value
Reset Value
0x9D
0x9B
203