C8051F022 Silicon Laboratories Inc, C8051F022 Datasheet - Page 211
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C8051F022
Manufacturer Part Number
C8051F022
Description
IC 8051 MCU 64K FLASH 100TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F02xr
Specifications of C8051F022
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
64
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x10b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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C8051F020/1/2/3
20.3. Frame and Transmission Error Detection
Frame error detection is available in the following modes when the SSTAT0 bit in register PCON is set to logic 1.
Note: The SSTAT0 bit must be logic 1 to access any of the status bits (FE0, RXOVR0, and TXCOL0). To access the
UART0 Mode Select bits (SM00, SM10, and SM20), the SSTAT0 bit must be logic 0.
All Modes:
The Transmit Collision bit (TXCOL0 bit in register SCON0) reads ‘1’ if user software writes data to the SBUF0 reg-
ister while a transmit is in progress. Note that the TXCOL0 bit also functions as the SM20 bit when the SSTAT0 bit in
register PCON is logic 0.
Modes 1, 2, and 3:
The Receive Overrun bit (RXOVR0 in register SCON0) reads ‘1’ if a new data byte is latched into the receive buffer
before software has read the previous byte. Note that the RXOVR0 bit also functions as the SM10 bit when the
SSTAT0 bit in register PCON is logic 0.
The Frame Error bit (FE0 in register SCON0) reads ‘1’ if an invalid (low) STOP bit is detected. Note that the FE0 bit
also functions as the SM00 bit when the SSTAT0 bit in register PCON is logic 0.
Rev. 1.4
211