C8051F022 Silicon Laboratories Inc, C8051F022 Datasheet - Page 223
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C8051F022
Manufacturer Part Number
C8051F022
Description
IC 8051 MCU 64K FLASH 100TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F02xr
Specifications of C8051F022
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
64
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x10b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Bits7-6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
SM01/FE1
R/W
Bit7
The function of these bits is determined by the SSTAT1 bit in register PCON.
If SSTAT1 is logic 1, these bits are UART1 status indicators as described in
If SSTAT1 is logic 0, these bits select the Serial Port Operation Mode as shown below.
SM01-SM11: Serial Port Operation Mode:
SM21: Multiprocessor Communication Enable.
If SSTAT1 is logic 1, this bit is a UART1 status indicator as described in
If SSTAT1 is logic 0, the function of this bit is dependent on the Serial Port Operation Mode.
Mode 0: No effect.
Mode 1: Checks for valid stop bit.
Modes 2 and 3: Multiprocessor Communications Enable.
REN1: Receive Enable.
This bit enables/disables the UART1 receiver.
0: UART1 reception disabled.
1: UART1 reception enabled.
TB81: Ninth Transmission Bit.
The logic level of this bit will be assigned to the ninth transmission bit in Modes 2 and 3. It is not used
in Modes 0 and 1. Set or cleared by software as required.
RB81: Ninth Receive Bit.
The bit is assigned the logic level of the ninth bit received in Modes 2 and 3. In Mode 1, if SM21 is
logic 0, RB81 is assigned the logic level of the received stop bit. RB8 is not used in Mode 0.
TI1: Transmit Interrupt Flag.
Set by hardware when a byte of data has been transmitted by UART1 (after the 8th bit in Mode 0, or
at the beginning of the stop bit in other modes). When the UART1 interrupt is enabled, setting this bit
causes the CPU to vector to the UART1 interrupt service routine. This bit must be cleared manually
by software
RI1: Receive Interrupt Flag.
Set by hardware when a byte of data has been received by UART1 (as selected by the SM21 bit).
When the UART1 interrupt is enabled, setting this bit causes the CPU to vector to the UART1 inter-
rupt service routine. This bit must be cleared manually by software.
SM01
SM11/RXOV1
0
0
1
1
R/W
0: Logic level of stop bit is ignored.
1: RI1 will only be activated if stop bit is logic level 1.
0: Logic level of ninth bit is ignored.
1: RI1 is set and an interrupt is generated only when the ninth bit is logic 1 and the received
address matches the UART1 address or the broadcast address.
Bit6
SM11
Figure 21.8. SCON1: UART1 Control Register
0
1
0
1
SM21/TXCOL1
Mode
R/W
Bit5
Mode 1: 8-Bit UART, Variable Baud Rate
Mode 3: 9-Bit UART, Variable Baud Rate
Mode 2: 9-Bit UART, Fixed Baud Rate
Mode 0: Synchronous Mode
REN1
R/W
Bit4
Rev. 1.4
TB81
R/W
Bit3
RB81
R/W
Bit2
C8051F020/1/2/3
R/W
TI1
Bit1
Section
Section
21.3.
R/W
RI1
Bit0
21.3.
SFR Address:
00000000
Reset Value
0xF1
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