HD64F3694FY Renesas Electronics America, HD64F3694FY Datasheet - Page 114

• Manufacturer Part Number: HD64F3694FY
• Description: IC H8 MCU FLASH 32K 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3694FY

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 6 Power-Down Modes
cleared, a transition is made to active mode when the LSON bit in SYSCR2 is 0, and a transition is
made to subactive mode when the bit is 1.
When the RES pin goes low, the system clock pulse generator starts. Since system clock signals
are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the
RES pin must be kept low until the pulse generator output stabilizes. After the pulse generator
output has stabilized, the CPU starts reset exception handling if the RES pin is driven high.
6.2.4
The operating frequency of subactive mode is selected from
SA0 bits in SYSCR2. After the SLEEP instruction is executed, the operating frequency changes to
the frequency which is set before the execution. When the SLEEP instruction is executed in
subactive mode, a transition to sleep mode, subsleep mode, standby mode, active mode, or
subactive mode is made, depending on the combination of SYSCR1 and SYSCR2. When the RES
pin goes low, the system clock pulse generator starts. Since system clock signals are supplied to
the entire chip as soon as the system clock pulse generator starts functioning, the RES pin must be
kept low until the pulse generator output stabilizes. After the pulse generator output has stabilized,
the CPU starts reset exception handling if the RES pin is driven high.
6.3
Operation in active mode is clocked at the frequency designated by the MA2, MA1, and MA0 bits
in SYSCR2. The operating frequency changes to the set frequency after SLEEP instruction
execution.
Rev.5.00 Nov. 02, 2005 Page 84 of 418
REJ09B0028-0500
Subactive Mode
Operating Frequency in Active Mode
W
/2,
W
/4, and
W
/8 by the SA1 and