HD64F3694FY Renesas Electronics America, HD64F3694FY Datasheet - Page 333

• Manufacturer Part Number: HD64F3694FY
• Description: IC H8 MCU FLASH 32K 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3694FY

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Register Name
General register B
General register C
General register D
Flash memory control register 1
Flash memory control register 2
Flash memory power control register FLPWCR 8
Erase block register 1
—
Flash memory enable register
—
Timer control register V0
Timer control/status register V
Timer constant register A
Timer constant register B
Timer counter V
Timer control register V1
Timer mode register A
Timer counter A
Serial mode register
Bit rate register
Serial control register 3
Transmit data register
Serial status register
Receive data register
—
A/D data register A
Abbre-
viation
FLMCR1 8
FLMCR2 8
EBR1
—
FENR
—
TCRV0
TCSRV
TCNTV
TCRV1
TMA
TCA
SMR
BRR
TDR
SSR
RDR
—
GRB
GRC
GRD
TCORA
TCORB
SCR3
ADDRA
Bit
No
—
8
—
8
8
8
8
8
8
8
8
8
8
8
8
8
—
16
16
16
8
8
16
Address
H'FF90
H'FF91
H'FF92
H'FF94 to
H'FF9A
H'FF9B
H'FF9C to
H'FF9F
H'FFA0
H'FFA4
H'FFA5
H'FFA6
H'FFA7
H'FFA8
H'FFA9
H'FFAB
H'FFAC
H'FFAE,
H'FFAF
H'FF8A
H'FF8C
H'FF8E
H'FF93
H'FFA1
H'FFA2
H'FFA3
H'FFAA
H'FFAD
H'FFB0
Rev.5.00 Nov. 02, 2005 Page 303 of 418
Module
Name
Timer W
Timer W
Timer W
ROM
ROM
ROM
ROM
—
ROM
—
Timer V
Timer V
Timer V
Timer V
Timer V
Timer V
Timer A
Timer A
SCI3
SCI3
SCI3
SCI3
SCI3
SCI3
—
A/D
converter
Section 20 List of Registers
Data
Bus
Width
16*
16*
16*
8
8
8
8
—
8
—
8
8
8
8
8
8
8
8
8
8
8
8
8
8
—
8
REJ09B0028-0500
2
2
2
Access
State
2
2
2
2
2
2
2
—
2
—
3
3
3
3
3
3
2
2
3
3
3
3
3
3
—
3