HD64F3694FY Renesas Electronics America, HD64F3694FY Datasheet - Page 260

IC H8 MCU FLASH 32K 48-LQFP

HD64F3694FY

Manufacturer Part Number
HD64F3694FY
Description
IC H8 MCU FLASH 32K 48-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet

Specifications of HD64F3694FY

Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI
Peripherals
PWM, WDT
Number Of I /o
29
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F3694FYJV
Manufacturer:
RENESAS/瑞萨
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20 000
Part Number:
HD64F3694FYV
Manufacturer:
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Quantity:
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Section 14 Serial Communication Interface 3 (SCI3)
14.8.4
In asynchronous mode, the SCI3 operates on a basic clock with a frequency of 16 times the
transfer rate. In reception, the SCI3 samples the falling edge of the start bit using the basic clock,
and performs internal synchronization. Receive data is latched internally at the rising edge of the
8th pulse of the basic clock as shown in figure 14.19.
Thus, the reception margin in asynchronous mode is given by formula (1) below.
M = (0.5 –
Where N : Ratio of bit rate to clock (N = 16)
Assuming values of F (absolute value of clock rate deviation) = 0 and D (clock duty) = 0.5 in
formula (1), the reception margin can be given by the formula.
M = {0.5 – 1/(2 16)} 100 [%] = 46.875%
However, this is only the computed value, and a margin of 20% to 30% should be allowed for in
system design.
Rev.5.00 Nov. 02, 2005 Page 230 of 418
REJ09B0028-0500
D : Clock duty (D = 0.5 to 1.0)
L : Frame length (L = 9 to 12)
F : Absolute value of clock rate deviation
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
Internal basic
clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
2N
Figure 14.19 Receive Data Sampling Timing in Asynchronous Mode
1
) –
D – 0.5
N
0
– (L – 0.5) F
8 clocks
Start bit
16 clocks
7
100(%)
15 0
D0
7
... Formula (1)
15 0
D1

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