HD6417032F20 Renesas Electronics America, HD6417032F20 Datasheet - Page 18

• Manufacturer Part Number: HD6417032F20
• Description: IC SUPERH MPU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

8.2
8.3
8.4
8.5
8.6
8.7
8.8
Rev. 7.00 Jan 31, 2006 page xvi of xxvi
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
Register Descriptions ........................................................................................................ 109
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
8.2.9
8.2.10 Parity Control Register (PCR) ............................................................................. 124
8.2.11 Notes on Register Access..................................................................................... 126
Address Space Subdivision ............................................................................................... 127
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
Accessing External Memory Space .................................................................................. 139
8.4.1
8.4.2
8.4.3
DRAM Interface Operation............................................................................................... 145
8.5.1
8.5.2
8.5.3
8.5.4
8.5.5
8.5.6
Address/Data Multiplexed I/O Space Access ................................................................... 162
8.6.1
8.6.2
8.6.3
Parity Check and Generation ............................................................................................ 164
Warp Mode ....................................................................................................................... 165
Features................................................................................................................ 103
Block Diagram..................................................................................................... 104
Pin Configuration................................................................................................. 105
Register Configuration......................................................................................... 106
Overview of Areas ............................................................................................... 107
Bus Control Register (BCR) ................................................................................ 109
Wait State Control Register 1 (WCR1)................................................................ 111
Wait State Control Register 2 (WCR2)................................................................ 113
Wait State Control Register 3 (WCR3)................................................................ 115
DRAM Area Control Register (DCR).................................................................. 117
Refresh Control Register (RCR) .......................................................................... 119
Refresh Timer Control/Status Register (RTCSR) ................................................ 121
Refresh Timer Counter (RTCNT)........................................................................ 122
Refresh Time Constant Register (RTCOR) ......................................................... 123
Address Spaces and Areas ................................................................................... 127
Bus Width ............................................................................................................ 129
Chip Select Signals (CS0–CS7) ........................................................................... 129
Shadows ............................................................................................................... 130
Area Descriptions................................................................................................. 132
Basic Timing........................................................................................................ 139
Wait State Control................................................................................................ 141
Byte Access Control ............................................................................................ 144
DRAM Address Multiplexing.............................................................................. 145
Basic Timing........................................................................................................ 147
Wait State Control................................................................................................ 149
Byte Access Control ............................................................................................ 151
DRAM Burst Mode.............................................................................................. 153
Refresh Control.................................................................................................... 158
Basic Timing........................................................................................................ 162
Wait State Control................................................................................................ 163
Byte Access Control ............................................................................................ 164