HD6417032F20 Renesas Electronics America, HD6417032F20 Datasheet - Page 227

• Manufacturer Part Number: HD6417032F20
• Description: IC SUPERH MPU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

External-Pin Round-Robin Mode: External-pin round-robin mode switches the priority levels of
channel 0 and channel 1, which are the channels that can receive transfer requests from external
pins DREQ0 and DREQ1. The priority levels are changed after each (byte or word) transfer on
channel 0 or channel 1 is completed. The channel which just finished the transfer rotates to the
bottom of the priority order. The priority levels of channels 2 and 3 do not change. The initial
priority order after a reset is channel 3 > channel 2 > channel 1 > channel 0.
Figure 9.5 shows how the priority order changes when channel 0 and channel 1 transfers are
requested simultaneously and a channel 0 transfer is requested again after both channels finish
their transfers. The DMAC operates as follows:
1. Transfer requests are generated simultaneously for channels 1 and 0.
2. Channel 1 has a higher priority, so the channel 1 transfer begins first (channel 0 waits for
3. When the channel 1 transfer ends, channel 1 becomes the lowest priority.
4. The channel 0 transfer begins.
5. When the channel 0 transfer ends, channel 0 becomes the lowest priority.
6. A channel 0 transfer request occurs again.
7. The channel 0 transfer begins.
8.
transfer).
When the channel 0 transfer ends, the priority order does not change, because channel 0 is
already the lowest priority.
Section 9 Direct Memory Access Controller (DMAC)
Rev. 7.00 Jan 31, 2006 page 199 of 658
REJ09B0272-0700