XC705B32CFNE Freescale Semiconductor, XC705B32CFNE Datasheet - Page 115

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XC705B32CFNE

Manufacturer Part Number
XC705B32CFNE
Description
IC MCU 2.1MHZ 32K OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of XC705B32CFNE

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SCI
Peripherals
POR, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
OTP
Eeprom Size
256 x 8
Ram Size
528 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Manufacturer:
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9.2.4
The following three functions: reset, STOP and WAIT, are not in the strictest sense interrupts. However,
they are acted upon in a similar manner. Flowcharts for STOP and WAIT are shown in
RESET: A reset condition causes the program to vector to its starting address, which is
STOP:
WAIT:
MC68HC05B6
Rev. 4.1
contained in memory locations $1FFE (MSB) and $1FFF (LSB). The I-bit in the
condition code register is also set, to disable interrupts.
The STOP instruction causes the oscillator to be turned off and the processor to ‘sleep’
until an external interrupt (IRQ) or occurs or the device is reset.
The WAIT instruction causes all processor clocks to stop, but leaves the timer clocks
running. This ‘rest’ state of the processor can be cleared by reset, an external interrupt
(IRQ), a timer interrupt or an SCI interrupt. There are no special WAIT vectors for these
individual interrupts.
Hardware controlled interrupt sequence
RESETS AND INTERRUPTS
Figure
Freescale
2.4.
9-11
9

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