XC705B32CFNE Freescale Semiconductor, XC705B32CFNE Datasheet - Page 62

• Manufacturer Part Number: XC705B32CFNE
• Description: IC MCU 2.1MHZ 32K OTP 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of XC705B32CFNE

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SCI
• Peripherals: POR, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 256 x 8
• Ram Size: 528 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5
5.2
The various functions of the timer are monitored and controlled using the timer control and status
registers described below.
5.2.1
The timer control register ($0012) is used to enable the input captures (ICIE), output compares
(OCIE), and timer overflow (TOIE) functions as well as forcing output compares (FOLV1 and
FOLV2), selecting input edge sensitivity (IEDG1) and levels of output polarity (OLV1 and OLV2).
ICIE — Input captures interrupt enable
If this bit is set, a timer interrupt is enabled whenever the ICF1 or ICF2 status flag (in the timer
status register) is set.
OCIE — Output compares interrupt enable
status register) is set.
TOIE — Timer overflow interrupt enable
If this bit is set, a timer interrupt is enabled whenever the TOF status flag (in the timer status
register) is set.
Freescale
5-4
If this bit is set, a timer interrupt is enabled whenever the OCF1 or OCF2 status flag (in the timer
Timer control (TCR)
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
Timer control and status
Timer control register (TCR)
–
–
–
Interrupt enabled.
Interrupt disabled.
Interrupt enabled.
Interrupt disabled.
Interrupt enabled.
Interrupt disabled.
Address
$0012
PROGRAMMABLE TIMER
bit 7
ICIE
OCIE
bit 6
TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0
bit 5
bit 4
bit 3
bit 2
bit 1
MC68HC05B6
bit 0
Rev. 4.1
on reset
State