R8A77850ADBGV Renesas Electronics America, R8A77850ADBGV Datasheet - Page 527

• Manufacturer Part Number: R8A77850ADBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

12.4.7
The SDRAM timing register 2 (DBTR2) is a readable/writable register. It is initialized only upon
power-on reset.
Initial value:
Initial value:
Bit
31 to 26 ⎯
25, 24
23 to 21 ⎯
R/W:
R/W:
BIt:
BIt:
SDRAM Timing Register 2 (DBTR2)
Bit Name
TRTP1 and
TRTP0
31
15
⎯
⎯
R
R
0
0
30
14
⎯
⎯
R
R
0
0
29
13
⎯
⎯
Initial
Value
All 0
01
All 0
R
R
0
0
28
12
⎯
⎯
R
R
0
0
RDWR3
R/W
27
⎯
11
R
0
0
R/W
R
R/W
R
RDWR2
R/W
26
10
⎯
R
0
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.
These bits set the READ-PRE command minimum time
constraint for the same bank. These bits should be set
according to the SDRAM specifications. The number of
cycles is the number of DDR clock cycles.
00: Setting prohibit (If specified, correct operation
01: 2 cycles
10: 3 cycles
11: Setting prohibit (If specified, correct operation
Reserved
These bits are always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.
tRTP (READ-PRE command minimum time) Setting Bits
TRTP1
RDWR1
R/W
R/W
25
0
9
1
cannot be guaranteed.)
cannot be guaranteed.)
TRTP0
RDWR0
R/W
R/W
24
1
8
1
23
⎯
⎯
R
R
0
7
0
Rev.1.00 Jan. 10, 2008 Page 495 of 1658
22
⎯
⎯
R
R
0
6
0
12. DDR2-SDRAM Interface (DBSC2)
21
⎯
⎯
R
R
0
5
0
TRC4
R/W
20
⎯
R
0
4
0
WRRD3
TRC3
R/W
R/W
19
0
3
0
REJ09B0261-0100
WRRD2
TRC2
R/W
R/W
18
1
2
0
WRRD1
TRC1
R/W
R/W
17
0
1
1
WRRD0
TRC0
R/W
R/W
16
0
0
1