R8A77850ADBGV Renesas Electronics America, R8A77850ADBGV Datasheet - Page 718

• Manufacturer Part Number: R8A77850ADBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 686 of 1658
REJ09B0261-0100
Bit
15, 14
13, 12
Bit Name
DM[1:0]
SM[1:0]
Initial
Value
00
00
R/W
R/W
R/W
Descriptions
Destination Address Mode 1, 0
Specify whether the DMA destination address is
incremented or decremented.
00: Destination address is fixed
01: Destination address is incremented
10: Destination address is decremented
11: Setting prohibited
For any setting (00, 01, or 10), specifying a transfer size
greater than the bus width divides bus cycles into two or
more, and increases the number of addresses for the
divided bus cycles.
Source Address Mode 1, 0
Specify whether the DMA source address is
incremented or decremented.
00: Source address is fixed
01: Source address is incremented
10: Source address is decremented
11: Setting prohibited
For any setting (00, 01, or 10), specifying a transfer size
greater than the bus width divides bus cycles into two or
more, and increases the number of addresses for the
divided bus cycles.
byte unit transfer: +1
word unit transfer: +2
longword unit transfer: +4
16-byte unit transfer: +16
32-byte unit transfer: +32
byte unit transfer: −1
word unit transfer: −2
longword unit transfer: −4
Setting prohibited in 16/32-byte unit transfer
byte unit transfer: +1
word unit transfer: +2
longword units transfer: +4
16-byte unit transfer: +16
32-byte unit transfer: +32
byte unit transfer: −1
word unit transfer: −2
longword unit transfer: −4
Setting prohibited in 16/32-byte unit transfer