PIC18F2510-E/SP Microchip Technology, PIC18F2510-E/SP Datasheet - Page 206
![IC MCU FLASH 16KX16 28-DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18F2510-E/SP
Manufacturer Part Number
PIC18F2510-E/SP
Description
IC MCU FLASH 16KX16 28-DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18LF2410-ISO.pdf
(376 pages)
4.PIC18LF2410-ISO.pdf
(8 pages)
5.PIC18LF2410-ISO.pdf
(16 pages)
6.PIC18LF2410-ISO.pdf
(6 pages)
7.PIC18LF2410-ISO.pdf
(6 pages)
8.PIC18LF2410-ISO.pdf
(8 pages)
Specifications of PIC18F2510-E/SP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-DIP (0.300", 7.62mm)
For Use With
DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- PIC16F616T-ISL PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18LF2410-ISO PDF datasheet #3
- PIC18LF2410-ISO PDF datasheet #4
- PIC18LF2410-ISO PDF datasheet #5
- PIC18LF2410-ISO PDF datasheet #6
- PIC18LF2410-ISO PDF datasheet #7
- PIC18LF2410-ISO PDF datasheet #8
- Current page: 206 of 376
- Download datasheet (7Mb)
PIC18F2X1X/4X1X
17.3
The Synchronous Master mode is entered by setting
the CSRC bit (TXSTA<7>). In this mode, the data is
transmitted in a half-duplex manner (i.e., transmission
and reception do not occur at the same time). When
transmitting data, the reception is inhibited and vice
versa. Synchronous mode is entered by setting bit
SYNC (TXSTA<4>). In addition, enable bit SPEN
(RCSTA<7>) is set in order to configure the TX and RX
pins to CK (clock) and DT (data) lines, respectively.
The Master mode indicates that the processor trans-
mits the master clock on the CK line. Clock polarity is
selected with the SCKP bit (BAUDCON<4>); setting
SCKP sets the Idle state on CK as high, while clearing
the bit sets the Idle state as low. This option is provided
to support Microwire devices with this module.
17.3.1
The EUSART transmitter block diagram is shown in
Figure 17-3. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The Shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available).
FIGURE 17-11:
DS39636D-page 208
RC7/RX/DT
pin
RC6/TX/CK pin
(SCKP = 0)
RC6/TX/CK pin
(SCKP = 1)
Write to
TXREG Reg
TXIF bit
(Interrupt Flag)
TRMT bit
TXEN bit
Note: Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words.
EUSART Synchronous
Master Mode
EUSART SYNCHRONOUS MASTER
TRANSMISSION
Q1 Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4
‘1’
Write Word 1
SYNCHRONOUS TRANSMISSION
bit 0
Write Word 2
bit 1
Word 1
bit 2
Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
status of the TSR register. TRMT is a read-only bit which
Once the TXREG register transfers the data to the TSR
register (occurs in one T
the TXIF flag bit (PIR1<4>) is set. The interrupt can be
enabled or disabled by setting or clearing the interrupt
enable bit, TXIE (PIE1<4>). TXIF is set regardless of
the state of enable bit TXIE; it cannot be cleared in
software. It will reset only when new data is loaded into
the TXREG register.
While flag bit TXIF indicates the status of the TXREG
register, another bit, TRMT (TXSTA<1>), shows the
is set when the TSR is empty. No interrupt logic is tied to
this bit so the user has to poll this bit in order to deter-
mine if the TSR register is empty. The TSR is not
mapped in data memory so it is not available to the user.
To set up a Synchronous Master Transmission:
1.
2.
3.
4.
5.
6.
7.
8.
bit 7
Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRG16
bit, as required, to achieve the desired baud rate.
Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
If interrupts are desired, set enable bit TXIE.
If 9-bit transmission is desired, set bit TX9.
Enable the transmission by setting bit TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the TXREG
register.
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
bit 0
Word 2
bit 1
© 2009 Microchip Technology Inc.
CY
), the TXREG is empty and
bit 7
‘1’
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