PIC18F2510-E/SP Microchip Technology, PIC18F2510-E/SP Datasheet - Page 251
PIC18F2510-E/SP
Manufacturer Part Number
PIC18F2510-E/SP
Description
IC MCU FLASH 16KX16 28-DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18LF2410-ISO.pdf
(376 pages)
4.PIC18LF2410-ISO.pdf
(8 pages)
5.PIC18LF2410-ISO.pdf
(16 pages)
6.PIC18LF2410-ISO.pdf
(6 pages)
7.PIC18LF2410-ISO.pdf
(6 pages)
8.PIC18LF2410-ISO.pdf
(8 pages)
Specifications of PIC18F2510-E/SP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-DIP (0.300", 7.62mm)
For Use With
DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- PIC16F616T-ISL PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18LF2410-ISO PDF datasheet #3
- PIC18LF2410-ISO PDF datasheet #4
- PIC18LF2410-ISO PDF datasheet #5
- PIC18LF2410-ISO PDF datasheet #6
- PIC18LF2410-ISO PDF datasheet #7
- PIC18LF2410-ISO PDF datasheet #8
- Current page: 251 of 376
- Download datasheet (7Mb)
22.5
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PIC
The user program memory is divided into five blocks.
One of these is a boot block of 2 Kbytes. The remainder
of the memory is divided into four blocks on binary
boundaries.
Each of the five blocks has three code protection bits
associated with them. They are:
FIGURE 22-5:
© 2009 Microchip Technology Inc.
®
devices.
Program Verification and
Code Protection
(PIC18F2410/4410)
Unimplemented
16 Kbytes
Boot Block
Read ‘0’s
Block 0
Block 1
CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2410/2510/4410/4510
MEMORY SIZE/DEVICE
(PIC18F2510/4510)
Unimplemented
Boot Block
32 Kbytes
Read ‘0’s
Block 0
Block 1
Block 2
Block 3
000000h
0007FFh
000800h
001FFFh
002000h
003FFFh
004000h
005FFFh
006000h
007FFFh
1FFFFFh
Address
Range
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 22-5 shows the program memory organization
for 16- and 32-Kbyte devices and the specific code
protection bit associated with each block.
Figure 22-6 shows the program memory organization
for 48 and 64-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 22-3.
(Unimplemented Memory Space)
PIC18F2X1X/4X1X
Block Code Protection
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
CP1, WRT1, EBTR1
CP2, WRT2, EBTR2
CP3, WRT3, EBTR3
Controlled By:
DS39636D-page 253
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