MCF5274LVM166 Freescale Semiconductor, MCF5274LVM166 Datasheet - Page 34

• Manufacturer Part Number: MCF5274LVM166
• Description: IC MPU 32BIT COLDF 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5274LVM166

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 166MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 61
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Operating Temperature Range: 0°C To +70°C
• Frequency Typ: 166MHz
• Rohs Compliant: Yes
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 166MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Electrical Characteristics
8.11
MII signals use TTL signal levels compatible with devices operating at 5.0 V or 3.3 V.
8.11.1
The receiver functions correctly up to a FECn_RXCLK maximum frequency of 25 MHz +1%. The
processor clock frequency must exceed twice the FECn_RXCLK frequency.
Table 18
Figure 16
8.11.2
Table 19
The transmitter functions correctly up to a FECn_TXCLK maximum frequency of 25 MHz +1%. The
processor clock frequency must exceed twice the FECn_TXCLK frequency.
34
Num
M1
M2
M3
M4
lists MII receive channel timings.
lists MII transmit channel timings.
Fast Ethernet AC Timing Specifications
shows MII receive signal timings listed in
FECn_RXDV
FECn_RXER
FECn_RXD[3:0] (inputs)
FECn_RXCLK (input)
MII Receive Signal Timing (FECn_RXD[3:0], FECn_RXDV,
FECn_RXER, and FECn_RXCLK)
MII Transmit Signal Timing (FECn_TXD[3:0], FECn_TXEN,
FECn_TXER, FECn_TXCLK)
FECn_RXD[3:0], FECn_RXDV, FECn_RXER to FECn_RXCLK
setup
FECn_RXCLK to FECn_RXD[3:0], FECn_RXDV, FECn_RXER
hold
FECn_RXCLK pulse width high
FECn_RXCLK pulse width low
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
Figure 16. MII Receive Signal Timing Diagram
Characteristic
Table 18. MII Receive Signal Timing
M1
M2
M3
Table
18.
M4
35%
35%
Min
5
5
Max
65%
65%
—
—
Freescale Semiconductor
FECn_RXCLK
FECn_RXCLK
period
period
Unit
ns
ns