MCF5274LVM166 Freescale Semiconductor, MCF5274LVM166 Datasheet - Page 35

• Manufacturer Part Number: MCF5274LVM166
• Description: IC MPU 32BIT COLDF 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5274LVM166

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 166MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 61
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Operating Temperature Range: 0°C To +70°C
• Frequency Typ: 166MHz
• Rohs Compliant: Yes
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 166MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Figure 17
8.11.3
Table 20
Figure 18
Freescale Semiconductor
Num
Num
M5
M6
M7
M8
M9
lists MII asynchronous inputs signal timing.
shows MII transmit signal timings listed in
shows MII asynchronous input timings listed in
FECn_TXD[3:0] (outputs)
FECn_TXEN
FECn_TXER
MII Async Inputs Signal Timing (FECn_CRS and FECn_COL)
FECn_CRS, FECn_COL minimum pulse width
FECn_TXCLK to FECn_TXD[3:0], FECn_TXEN, FECn_TXER
invalid
FECn_TXCLK to FECn_TXD[3:0], FECn_TXEN, FECn_TXER
valid
FECn_TXCLK pulse width high
FECn_TXCLK pulse width low
FECn_TXCLK (input)
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
FECn_CRS
FECn_COL
Table 20. MII Asynchronous Input Signal Timing
Figure 17. MII Transmit Signal Timing Diagram
Figure 18. MII Async Inputs Timing Diagram
Characteristic
Characteristic
Table 19. MII Transmit Channel Timing
M5
M6
M7
Table
M9
Table
19.
20.
M8
35%
35%
Min
Min
1.5
—
5
Max
65%
65%
Max
25
—
—
Electrical Characteristics
FECn_TXCLK period
FECn_TXCLK period
FECn_TXCLK period
Unit
Unit
ns
ns
35