DSP56F807VF80 Freescale Semiconductor, DSP56F807VF80 Datasheet - Page 12

• Manufacturer Part Number: DSP56F807VF80
• Description: IC DSP 80MHZ 60K FLASH 160-BGA
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxr

Specifications of DSP56F807VF80

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 136KB (68K x 16)
• Program Memory Type: FLASH
• Ram Size: 6K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-MAPBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

2.5 Interrupt and Program Control Signals
12
No. of
No. of
No. of
Pins
Pins
Pins
16
1
1
1
1
1
1
Signal
Name
D0–D15
Signal
WR
Name
RD
Signal
PS
DS
Name
IRQA
IRQB
Signal
Output
Output
Output
Output
Type
Input/O
(Schmitt)
(Schmitt)
Signal
Type
utput
Signal
Type
Input
Input
Table 2-9 Interrupt and Program Control Signals
State During
Tri-stated
Tri-stated
Tri-stated
Tri-stated
Reset
State During
56F807 Technical Data Technical Data, Rev. 16
State During
Tri-stated
Reset
Table 2-8 Bus Control Signals
Reset
Input
Input
Table 2-7 Data Bus Signals
Program Memory Select—PS is asserted low for external program
memory access.
Data Memory Select—DS is asserted low for external data memory
access.
Write Enable—WR is asserted during external memory write cycles.
When WR is asserted low, pins D0–D15 become outputs and the device
puts data on the bus. When WR is deasserted high, the external data is
latched inside the external device. When WR is asserted, it qualifies the
A0–A15, PS, and DS pins. WR can be connected directly to the WE pin of
a Static RAM.
Read Enable—RD is asserted during external memory read cycles. When
RD is asserted low, pins D0–D15 become inputs and an external device is
enabled onto the device’s data bus. When RD is deasserted high, the
external data is latched inside the device. When RD is asserted, it qualifies
the A0–A15, PS, and DS pins. RD can be connected directly to the OE pin
of a Static RAM or ROM.
Data Bus— D0–D15 specify the data for external program or data
memory accesses. D0–D15 are tri-stated when the external bus is
inactive. Internal pullups may be active.
External Interrupt Request A—The IRQA input is a synchronized
external interrupt request that indicates that an external device is
requesting service. It can be programmed to be level-sensitive or
negative-edge-triggered.
External Interrupt Request B—The IRQB input is an external
interrupt request that indicates that an external device is requesting
service. It can be programmed to be level-sensitive or
negative-edge-triggered.
Signal Description
Signal Description
Signal Description
Freescale Semiconductor