MCF5272CVM66 Freescale Semiconductor, MCF5272CVM66 Datasheet - Page 182

• Manufacturer Part Number: MCF5272CVM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Interrupt Controller
7.2.5
The programmable interrupt wakeup register (PIWR),
sources are capable of causing the CPU to wake up from low-power SLEEP or STOP modes when their
source is active. All sources are disabled on reset. Note that only the external interrupt pins INT[6:1] can
wake up the CPU from STOP mode.
If more than one interrupt source has the same interrupt priority level (IPL) programmed in the ICRs, the
interrupt controller daisy chains the interrupts with the priority order following the bit placement in the
PIWR, with INT1 having the highest priority and SWTO having the lowest priority as shown in
Table 7-6
7-8
31–4
Bits
3–0
Address
Reset
Reset
Reset
Reset
describes PIWR fields.
Field
Field
Field
Field
R/W
R/W
R/W
R/W
Field
Programmable Interrupt Wakeup Register (PIWR)
—
—
UART1
USB4
QSPI
INT1
31
23
15
7
0 Interrupt cannot wake up the CPU when interrupt source is active.
1 Interrupt wakes up the CPU from low-power modes.
Reserved, should be cleared.
MCF5272 ColdFire
Figure 7-8. Programmable Interrupt Wakeup Register (PIWR)
UART2
USB5
INT2
INT5
30
22
14
6
Table 7-6. PIWR Field Descriptions
PLI_P
USB6
INT3
INT6
®
29
21
13
5
Integrated Microprocessor User’s Manual, Rev. 3
SWTO
PLI_A
USB7
INT4
28
20
12
4
MBAR+0x038
1111_1111
1111_1111
1111_1111
1111_0000
Figure
R/W
R/W
R/W
R/W
Description
TMR0
USB0
DMA
27
19
11
3
7-8, is used to specify which interrupt
TMR1
USB1
ERx
26
18
10
—
TMR2
USB2
ETx
25
17
9
Freescale Semiconductor
TMR3
ENTC
USB3
24
16
8
0
Figure
7-8.