MCF5272CVM66 Freescale Semiconductor, MCF5272CVM66 Datasheet - Page 330

• Manufacturer Part Number: MCF5272CVM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Physical Layer Interface Controller (PLIC)
13.5.22 Clock Select Register (PCSR)
All bits in this register are read/write and are cleared on hardware or software reset.
PCSR controls the PLIC clock generation block. Please refer to
for certain restrictions on the use of the clock generation block.
13-34
14–8
Bits
7–6
5–3
2–0
15
Reset
Field NBP
Addr
R/W
15
CMULT
Name
FDIV
NBP
CKI
—
14
MCF5272 ColdFire
Non-bypass mode select for the clock generation module.
0 The clock generation module is bypassed. Gen_FSC and GDCL are connected to FSC0 and
1 Selects non-bypassed mode. Gen_FSC and GDCL are synthesized from the incoming FSC0
Reserved, should be cleared.
Clock select Input. Selects the source clock for the clock generation block.
00 DCL0
01 FSC0
1x Reserved
FSC divide. Sets the divide ratio between GDCL and Gen_FSC.
000 ÷4
001 ÷8
010 ÷16
011 ÷32
100 ÷64
101 ÷128
110 ÷192
111 ÷256
Clock multiplication ratio. Sets the ratio of the reference clock frequency to the GDCL frequency.
000 x 2
001 x 4
010 x 8
011 x 16
100 x 32
101 x 64
110 x 128
111 x 256
—
DCL0.
or DCL0.
Figure 13-34. Clock Select Register (PCSR)
Table 13-17. PCSR Field Descriptions
8
®
Integrated Microprocessor User’s Manual, Rev. 3
7
CKI
0000_0000_0000_0000
6
MBAR + 0x39E
Read/Write
5
Description
FDIV
Section 13.3, “PLIC Timing
3
2
CMULT
Freescale Semiconductor
Generator,”
0