MCF5272CVM66 Freescale Semiconductor, MCF5272CVM66 Datasheet - Page 273

• Manufacturer Part Number: MCF5272CVM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

12.3.2.10 USB Endpoint 0 IN Configuration Register (IEP0CFG)
Figure 12-13
Table 12-11
maximum packet size for endpoint 0 is eight bytes. Writing to the register resets the FIFO. Any data in the
FIFO are discarded, and the associated EPnDP register is also reset.
Freescale Semiconductor
31–22
20–11
Bits
9–0
21
10
Bits
2
1
0
Reset
Reset
Field
Field
Addr
R/W
R/W
MAX_PACKET
FIFO_ADDR
FIFO_SIZE
lists field descriptions for the IEP0CFG register. Only longword writes are allowed. The
Name
HALT_ST
shows the USB Endpoint 0 IN configuration (IEP0CFG) register.
31
15
—
—
Name
DIR
—
Figure 12-13. USB Endpoint 0 IN Configuration Register (IEP0CFG)
FIFO_SIZE
MCF5272 ColdFire
Maximum packet size. Must be written with the maximum packet size defined in the device
descriptor for endpoint 0 or the endpoint descriptors for other endpoints.
Reserved, should be cleared.
Size of the FIFO. Sets the depth of the FIFO buffer for the endpoint. The FIFO size must be a power
of 2. For non-isochronous endpoints, the FIFO size must be at least two times the maximum packet
size.
Reserved, should be cleared.
Starting address in the FIFO buffer memory for the endpoint’s FIFO. Reading this field returns the
current write pointer for IN endpoints or the read pointer for OUT endpoints for the FIFO.
Current endpoint 0 halt status. Indicates whether endpoint 0 is currently halted or active. Endpoint
0 is halted if there is an error processing a request. A halt is cleared automatically by a SETUP
packet.
1 Endpoint 0 halted
0 Endpoint 0 active
Current endpoint 0 direction. Indicates whether endpoint 0 is currently accessed as an IN or OUT
endpoint.
1 The endpoint is configured as an IN endpoint
0 The endpoint is configured as an OUT endpoint
Reserved, should be cleared.
Table 12-11. IEP0CFG Field Descriptions
Table 12-10. EP0SR Field Descriptions
MAX_PACKET
11
®
Integrated Microprocessor User’s Manual, Rev. 3
—
10
0000_0000_0000_0000
0000_0000_0000_0000
9
MBAR + 0x1028
R/W
R/W
Descriptions
Descriptions
22
FIFO_ADDR
—
21
20
FIFO_SIZE
Universal Serial Bus (USB)
16
0
12-15