SC68C652BIB48,157 NXP Semiconductors, SC68C652BIB48,157 Datasheet - Page 16

• Manufacturer Part Number: SC68C652BIB48,157
• Description: IC UART DUAL 48LQFP
• Manufacturer: NXP Semiconductors

Specifications of SC68C652BIB48,157

• Features: 2 Channels
• Number Of Channels: 2, DUART
• Fifo's: 32 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 48-LFQFP
• Voltage: 2.25 V ~ 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935278766157; SC68C652BIB48; SC68C652BIB48

NXP Semiconductors
SC68C652B_2
Product data sheet
7.1 Transmit Holding Register (THR) and Receive Holding Register (RHR)
7.2 Interrupt Enable Register (IER)
The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and
Transmit Shift Register (TSR). The status of the THR is provided in the Line Status
Register (LSR). Writing to the THR transfers the contents of the data bus (D[7:0]) to the
TSR and UART via the THR, providing that the THR is empty. The THR empty flag in the
LSR register will be set to a logic 1 when the transmitter is empty or when data is
transferred to the TSR. Note that a write operation can be performed when the THR
empty flag is set (logic 0 = at least one byte in FIFO/THR, logic 1 = FIFO/THR empty).
The serial receive section also contains an 8-bit Receive Holding Register (RHR) and a
Receive Serial Shift Register (RSR). Receive data is removed from the SC68C652B and
receive FIFO by reading the RHR register. The receive section provides a mechanism to
prevent false starts. On the falling edge of a start or false start bit, an internal receiver
counter starts counting clocks at the 16 clock rate. After 7
should be shifted to the center of the start bit. At this time the start bit is sampled, and if it
is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver
from assembling a false character. Receiver status codes will be posted in the LSR.
The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter
empty, line status and modem status registers. These interrupts would normally be seen
on the IRQ output pin.
Table 10.
Bit
7
6
5
4
3
Symbol
IER[7]
IER[6]
IER[5]
IER[4]
IER[3]
Interrupt Enable Register bits description
Rev. 02 — 2 November 2009
Description
CTS interrupt
RTS interrupt
Xoff interrupt
Sleep mode
Modem Status Interrupt. This interrupt will be issued whenever there is a
modem status change as reflected in MSR[3:0].
logic 0 = disable the CTS interrupt (normal default condition)
logic 1 = enable the CTS interrupt. The SC68C652B issues an interrupt
when the CTSn pin transitions from a logic 0 to a logic 1.
logic 0 = disable the RTS interrupt (normal default condition)
logic 1 = enable the RTS interrupt. The SC68C652B issues an interrupt
when the RTSn pin transitions from a logic 0 to a logic 1.
logic 0 = disable the software flow control, receive Xoff interrupt (normal
default condition)
logic 1 = enable the software flow control, receive Xoff interrupt
logic 0 = disable Sleep mode (normal default condition)
logic 1 = enable Sleep mode
logic 0 = disable the modem status register interrupt (normal default
condition)
logic 1 = enable the modem status register interrupt
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
1
2
clocks, the start bit time
SC68C652B
© NXP B.V. 2009. All rights reserved.
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