SC68C652BIB48,157 NXP Semiconductors, SC68C652BIB48,157 Datasheet - Page 30

• Manufacturer Part Number: SC68C652BIB48,157
• Description: IC UART DUAL 48LQFP
• Manufacturer: NXP Semiconductors

Specifications of SC68C652BIB48,157

• Features: 2 Channels
• Number Of Channels: 2, DUART
• Fifo's: 32 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 48-LFQFP
• Voltage: 2.25 V ~ 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935278766157; SC68C652BIB48; SC68C652BIB48

NXP Semiconductors
10. Dynamic characteristics
Table 29.
T
[1]
[2]
[3]
[4]
SC68C652B_2
Product data sheet
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
t
t
t
t
d1
d2
d3
d4
d6
d7
d8
d9
d10
d11
d12
d13
d14
d15
d16
d17
d18
h2
h3
h4
WH
WL
XTAL
(RESET)
su1
su2
w1
amb
RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches.
Applies to external clock; crystal oscillator max 24 MHz.
Reset pulse must happen when CS is inactive.
f
= 40 C to +85 C; tolerance of V
XTAL
Parameter
R/W to chip select
read cycle delay
delay from CS to data
data disable time
write cycle delay
delay from write to output
delay to set interrupt from modem
input
delay to reset interrupt from read
delay from stop to set interrupt
delay from read to reset interrupt
delay from start to set interrupt
delay from write to transmit start
delay from write to reset interrupt
delay from stop to set RXRDY
delay from read to reset RXRDY
delay from write to set TXRDY
delay from start to reset TXRDY
R/W hold time from CS
data hold time
address hold time
pulse width HIGH
pulse width LOW
clock speed
RESET pulse width
address set-up time
data set-up time
CS strobe width
=
Dynamic characteristics
-------------- -
t
w clk
1
CC
10 %, unless specified otherwise.
Conditions
25 pF load
25 pF load
25 pF load
25 pF load
25 pF load
25 pF load
25 pF load
Rev. 02 — 2 November 2009
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
[2][3]
[4]
8T
Min
RCLK
200
10
20
25
10
15
15
10
10
10
16
77
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
CC
[1]
= 2.5 V
24T
16T
1T
1T
Max
100
100
100
RCLK
100
100
100
RCLK
100
100
77
15
RCLK
RCLK
48
-
-
-
-
-
-
-
-
-
-
-
-
[1]
[1]
[1]
[1]
8T
V
SC68C652B
Min
RCLK
200
CC
10
20
25
10
15
15
10
16
30
6
6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
= 3.3 V and 5 V
[1]
© NXP B.V. 2009. All rights reserved.
24T
16T
1T
1T
Max
RCLK
100
RCLK
26
15
33
24
24
29
RCLK
70
75
70
RCLK
80
-
-
-
-
-
-
-
-
-
-
-
-
[1]
[1]
[1]
[1]
30 of 43
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns