SC68C652BIB48,157 NXP Semiconductors, SC68C652BIB48,157 Datasheet - Page 22

• Manufacturer Part Number: SC68C652BIB48,157
• Description: IC UART DUAL 48LQFP
• Manufacturer: NXP Semiconductors

Specifications of SC68C652BIB48,157

• Features: 2 Channels
• Number Of Channels: 2, DUART
• Fifo's: 32 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 48-LFQFP
• Voltage: 2.25 V ~ 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935278766157; SC68C652BIB48; SC68C652BIB48

NXP Semiconductors
SC68C652B_2
Product data sheet
7.5 Line Control Register (LCR)
The Line Control Register is used to specify the asynchronous data communication
format. The word length, the number of stop bits, and the parity are selected by writing the
appropriate bits in this register.
Table 16.
Table 17.
Table 18.
Table 19.
Bit
7
6
5:3
2
1:0
LCR[5]
X
X
0
0
1
LCR[2]
0
1
1
LCR[1]
0
0
1
1
Line Control Register bits description
LCR[5:3] parity selection
LCR[2] stop bit length
LCR[1:0] word length
LCR[4]
X
0
1
0
1
Word length
5, 6, 7, 8
5
6, 7, 8
LCR[0]
0
1
0
1
Symbol
LCR[7]
LCR[6]
LCR[5:3]
LCR[2]
LCR[1:0]
Rev. 02 — 2 November 2009
LCR[3]
0
1
1
1
1
Description
Divisor latch enable. The internal baud rate counter latch and Enhanced
Feature mode enable.
Set break. When enabled, the Break control bit causes a break
condition to be transmitted (the TXn output pin is forced to a logic 0
state). This condition exists until disabled by setting LCR[6] to a logic 0.
Set parity; even parity; parity enable. Programs the parity conditions
(see
Stop bits. The length of stop bit is specified by this bit in conjunction with
the programmed word length (see
Word length bits 1, 0. These two bits specify the word length to be
transmitted or received (see
logic 0 = divisor latch disabled (normal default condition)
logic 1 = divisor latch enabled
logic 0 = no break condition (normal default condition)
logic 1 = forces the transmitter output pin (TXn) to a logic 0 for
alerting the remote receiver to a line break condition
logic 0 or cleared = default condition
logic 0 or cleared = default condition
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
Table
Word length
5
6
7
8
Stop bit length (bit times)
1
1
2
1
2
17).
Parity selection
no parity
odd parity
even parity
forced parity ‘1’
forced parity ‘0’
Table
Table
19).
18).
SC68C652B
© NXP B.V. 2009. All rights reserved.
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